Group A Connections - Clock Signals - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Making Connections in the SRU
Group A Connections – Clock Signals
Group A is used to route signals to clock inputs. The SPORTs clock
inputs (when the SPORTs are in clock slave mode), the clock inputs to
the eight IDP channels and the two Precision Clock Generators (PCGs)
external sources are selected from the list of Group A sources and set in
the Group A registers. When channel 0 of the IDP is configured for
PDAP input, the clock source set here is used as the parallel word latch
instead of the serial bit clock

All unused clock inputs should be set to logic LOW. Any IDP
channels that receive clock signals set here will send data to the
FIFO. When a SPORT is used as a clock master, setting the
unused SPORT clock input to logic LOW improves signal integ-
rity. The registers, and input and output signals for group A are
shown in
Table 12-2. Group A Sources – Serial Clock
Signal Inputs
Clock Register
SRU_CLK0
SRU_CLK1
SRU_CLK2
SRU_CLK3
12-18
(Table
Table 12-6.
Bit field
SPORT0_CLK_I
SPORT1_CLK_I
SPORT2_CLK_I
SPORT3_CLK_I
SPORT4_CLK_I
SPORT5_CLK_I
IDP0_CLK_I
IDP1_CLK_I
IDP2_CLK_I
IDP3_CLK_I
IDP4_CLK_I
IDP5_CLK_I
IDP6_CLK_I
IDP7_CLK_I
PCG_EXTA_I
PCG_EXTB_I
ADSP-2126x SHARC Processor Hardware Reference
12-2).
Signal Sources
• 20 External Pins (DAI_PBxx_O)
• 6 Serial Port x Clock Outs
(SPORTx_CLK_O)
• 2 Precision Clock Generators (A/B)
(PCG_CLKx_O)
• 2 Logic Level (HIGH/LOW)
Options