Delayed Branches - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Delayed Branches

The instruction pipeline influences how the sequencer handles delayed
branches. For immediate branches in which
instructions are not specified as delayed branches
cycles are lost (
from the new branch.
As shown in Table 3-2
after the branch, which are in the fetch and decode stages. For a
decode address (the address of the instruction after the
address. During the two lost
the first instruction at the branch address.
In the illustrations that follow, shading indicates aborted instructions,
which are followed by
Table 3-2. Pipelined Execution Cycles for Immediate Branch
(Jump/Call)
Cycles
Execute
Decode
Fetch
1. N + 1 suppressed
2. For call, N + 1 pushed onto PC stack
3. N + 2 suppressed
Table 3-3. Pipelined Execution Cycles for Immediate Branch (Return)
Cycles
Execute
Decode
Fetch
1. N + 1 suppressed
2. R (N + 1 in Figure 2-14 on page...)popped from PC stack
3. N + 2 suppressed
ADSP-2126x SHARC Processor Hardware Reference
) as the pipeline empties and refills with instructions
NOP
and Table
NOP
instructions.
NOP
1 2
N NOP
1
N + 1–>NOP N + 2–>NOP
N + 2 2
J
1 2
N NOP
1
N + 1–>NOP N + 2–>NOP
N + 2 2
R
Program Sequencer
and
JUMP
(DB)
3-2, the DSP aborts the two instructions
cycles, the pipeline fetches and decodes
3
NOP
3 2
J
J + 1
3
NOP
3 R
R + 1
/
CALL RETURN
, two instruction
, the
CALL
) is the return
CALL
4
2
J
J + 1
J + 2
4
R
R + 1
R + 2
3-13