Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 582

Enabling a Timer
When the timer detects a first leading edge, it starts incrementing. When
it detects the trailing edge of a waveform, the timer captures the current
value of the Count register (=
width registers. At the next leading edge, the timer transfers the current
value of the Count register (=
The Count registers are reset to 0x0000 0001 again, and the timer contin-
ues counting until it is either disabled or the count value reaches
0xFFFF FFFF.
In this mode, software can measure both the pulse width and the pulse
period of a waveform. To control the definition of the leading edge and
trailing edge of the
or cleared. If the
falling edge, the Count register is captured to the Width register on the
rising edge, and the Period register is captured on the next falling edge.
The bit in the
PRDCNT
rupt is generated when the pulse width or pulse period is captured. If the
bit is set, the Interrupt Latch bit (
PRDCNT
period value is captured. If the
set when the pulse width value is captured.
If the bit is cleared, the first period value has not yet been mea-
PRDCNT
sured when the first interrupt is generated. Therefore, the period value is
not valid. If the interrupt service routine reads the period value anyway,
the timer returns a period value of zero. When the period expires, the
period value is loaded in the
A timer interrupt (if enabled) is also generated if the Count register
reaches a value of 0xFFFF FFFF. At that point, the timer is disabled auto-
matically, and the
The and
TIMxIRQ
clear them.
14-12
TMxCNT
TMxCNT
signal, the
TIMERx
bit is cleared, the measurement is initiated by a
PULSE
register controls whether an enabled inter-
TMxCTL
PRDCNT
TMxPRD
Status bit is set, indicating a count overflow.
TIMxOVF
bits are sticky bits, and software must explicitly
TMxOVF
ADSP-2126x SHARC Processor Hardware Reference
/2) and transfers it into the
/2) into the
TMxPRD
bit in the
PULSE TMxCTL
) gets set when the pulse
TIMxIRQ
bit is cleared, the
register.
TMxW
period register.
register is set
bit gets
TIMxIRQ