Polling/Status Driven I/O - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Table 7-1. DMA Interrupt Vector Locations (Cont'd)
Associated Register(s)
IRPTL/IMASK
(high priority option)
LIRPTL
(low priority option)
IRPTL/IMASK
(high priority option)
LIRPTL
(low priority option)
The SPI has two interrupts—a lower priority option (
priority option (
are higher and lower than serial ports.
The DAI also has two interrupts—the lower priority option (
higher priority option (
ties that are higher and lower than serial ports.

Polling/Status Driven I/O

The second method of controlling I/O is through status polling. The I/O
processor monitors the status of data transfers on DMA channels and indi-
cates interrupt status in the
registers. Note that because polling uses processor resources it is not as
efficient as an interrupt-driven system. Also note that polling the DMA
status registers reduces I/O bandwidth. The following provide more infor-
mation on the registers that control and monitor I/O processes.
• All the bits in
rupt Latch Register (IRPTL)" on page A-25
Register (LIRPTL)" on page
ADSP-2126x SHARC Processor Hardware Reference
Bits Vector
Address
11 0x2C
6 0x5C
11 0x2C
6 0x5C
). This allows two interrupts to have priorities that
SPIHI
). This allows two interrupts to have priori-
DAIHI
,
IRPTL
and
IRPTL LIRPTL
Interrupt DMA
Name Channel
DAIHI 18
DAILI
DAIHI 19
DAILI
,
LIRPTL DAI_IRPTL_H
registers are shown in the
and
A-30.
I/O Processor
Data Buffer
IDP_FIF0
IDP_FIF0
) and a higher
SPILI
) and
DAILI
, and
DAI_IRPTL_L
"Inter-
"Interrupt
7-7