SPI DMA Registers
There are five SPI DMA-specific registers which are described in the fol-
lowing sections.
SPI DMA Configuration (SPIDMAC) Register
The SPI DMA Configuration Register contains the control bits for SPI
DMA transfers.
register.
The
,
SPIMME
SPIUNF
if the corresponding
clear these bits, clear corresponding bits in the
figure a new DMA
ADSP-2126x SHARC Processor Hardware Reference
Table A-30
provides the bit descriptions for the
, and
bits are sticky; these bits remain set even
SPIOVF
bits (
SPISTAT
Registers Reference
,
, and
MME
TUNF
ROVF
SPISTAT
SPIDMAC
) are cleared. To
, register then con-
A-103
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