Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 776

I/O Processor Registers
provides a reset bit that zeros any data waiting in the packing unit to be
latched into the FIFO. The
strobe when asserted, and then automatically clears. Therefore, this bit
always returns a value of zero when read. Bit 26 of the
ter selects between the two sets of pins that may be used as the parallel
input port. When the
read from the
AD[15:Ø]
the upper 16 bits are read from the
Note that the four LSBs of the parallel data acquisition port input are not
multiplexed, and this input value is always read from the DAI pins,
.
DAI_P[4:1]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
IDP_PDAP_EN
IDP_PDAP_RESET
IDP_PDAP_CLKEDGE
IDP_PDAP_PACKINGX
IDP_PORT_SELECT
Reserved
15 14 13 12 11 10
IDP_P16_PDAPMASK
IDP_P15_PDAPMASK
IDP_P14_PDAPMASK
IDP_P13_PDAPMASK
IDP_P12_PDAPMASK
IDP_P11_PDAPMASK
IDP_P10_PDAPMASK
IDP_P09_PDAPMASK
Figure A-67. IDP_PDAP_CTL Register
A-154
RESET
IDP_PDAP_CTL[26]
pins. When the
0 0 0 0 0 0 0
9 8
0 0 0 0 0 0 0 0
ADSP-2126x SHARC Processor Hardware Reference
bit (bit 30) causes the reset circuit to
bit is set, the upper 16 bits are
IDP_PDAP_CTL[26]
pins.
DAI_P[20:5]
0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
regis-
IDP_PDAP_CTL
bit is cleared,
IDP_P17_PDAPMASK
IDP_P18_PDAPMASK
IDP_P19_PDAPMASK
IDP_P20_PDAPMASK
IDP_P01_PDAPMASK
IDP_P02_PDAPMASK
IDP_P03_PDAPMASK
IDP_P04_PDAPMASK
IDP_P05_PDAPMASK
IDP_P06_PDAPMASK
IDP_P07_PDAPMASK
IDP_P08_PDAPMASK