Sisd, Simd, And Broadcast Load Modes; Single- And Dual-Data Accesses - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Accessing Memory
Mode 2 Register Control Bits
The following bits in the
• Illegal IOP Register Access Enable.
detection of IOP register access (if 1) or disables detection (if 0).
• Unaligned 64-bit Memory Access Enable.
enables detection of uneven address memory access (if 1) or dis-
ables detection (if 0).

SISD, SIMD, and Broadcast Load Modes

These modes influence memory accesses. For a comparison of their effects,
see the examples in
"Secondary Processor Element (PEy)" on page
Broadcast load mode is a hybrid between SISD and SIMD modes that
transfers dual-data under special conditions. For examples of broadcast
transfers, see"Internal Memory Access Listings" on page
information on broadcast load mode, see
page 5-20.

Single- and Dual-Data Accesses

The number of transfers that occur in a cycle influences the data access
operation. As described in
ports single cycle, dual-data accesses to and from internal memory for
register-to-memory and memory-to-register transfers. Dual-data accesses
occur over the PM and DM bus and act independent of SIMD/SISD.
Though only available for transfers between memory and data registers,
dual-data transfers are extremely useful because they double the data
throughput over single-data transfers.
5-28
register control memory access modes:
MODE2
"Internal Memory Access Listings" on page
"DSP Architecture" on page
ADSP-2126x SHARC Processor Hardware Reference
Bit 20 (
MODE2 IIRAE
Bit 21 (
MODE2
5-19.
5-30. For more
"Broadcast Register Loads" on
5-2, the DSP sup-
) enables
)
U64MAE
5-30. and