During the
FPACK
non-overflow clears it. During the
cleared. The
SZ
Fixed-Point Formats
The DSP supports two 32-bit fixed-point formats—fractional and integer.
In both formats, numbers can be signed (twos-complement) or unsigned.
The four possible combinations are shown in
format, there is an implied binary point to the left of the most significant
magnitude bit. In integer format, the binary point is understood to be to
the right of the LSB. Note that the sign bit is negatively weighted in a
twos-complement format.
ALU outputs always have the same width and data format as the inputs.
The multiplier, however, produces a 64-bit product from two 32-bit
inputs. If both operands are unsigned integers, the result is a 64-bit
unsigned integer. If both operands are unsigned fractions, the result is a
64-bit unsigned fraction. These formats are shown in
If one operand is signed and the other unsigned, the result is signed. If
both inputs are signed, the result is signed and automatically shifted left
one bit. The LSB becomes zero and bit 62 moves into the sign bit posi-
tion. Normally bit 63 and bit 62 are identical when both operands are
signed. (The only exception is full-scale negative multiplied by itself.)
Thus, the left-shift normally removes a redundant sign bit, increasing the
precision of the most significant product. Also, if the data format is frac-
tional, a single bit left-shift renormalizes the MSP to a fractional format.
The signed formats with and without left-shifting are shown in
Figure
2-6.
The multiplier has an 80-bit accumulator to allow the accumulation of
64-bit products. For more information on the multiplier and accumula-
tor, see
"Multiply Accumulator (Multiplier)" on page
ADSP-2126x SHARC Processor Hardware Reference
operation, an overflow sets the
and
conditions are cleared by both instructions.
SS
Processing Elements
condition and
SV
operation, the
FUNPACK
Figure
2-5. In the fractional
condition is
SV
Figure
2-7.
2-23.
2-9
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