Program Counter Register (Pc - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Table A-10. LIRPTL Register Bit Descriptions (Cont'd)
Bit Name
21 P7IMSKP
22 P8IMSKP
23 P9IMSKP
24 P10IMSKP
25 P11IMSKP
26 P12IMSKP
27 P13IMSKP
28 P17IMSKP
29 P18MSKP
31–30 Reserved

Program Counter Register (PC)

The register is a non-memory-mapped, universal register (
PC
The Program Counter register is the last stage in the fetch-decode-execute
instruction pipeline and contains the 24-bit address of the instruction that
the DSP executes on the next cycle. The
Counter Stack,
addresses. All addresses generated by the sequencer are 24-bit program
memory instruction addresses.
As shown in Figure
but the program sequencer only generates 24-bit addresses over the PM
bus.
ADSP-2126x SHARC Processor Hardware Reference
Definition
Programmable Interrupt Mask Pointer 7. See P6IMSKP.
Programmable Interrupt Mask Pointer 8. See P6IMSKP.
Programmable Interrupt Mask Pointer 9. See P6IMSKP.
Programmable Interrupt Mask Pointer 10. See P6IMSKP.
Programmable Interrupt Mask Pointer 11. See P6IMSKP.
Programmable Interrupt Mask Pointer 12. See P6IMSKP.
Programmable Interrupt Mask Pointer 13. See P6IMSKP.
Programmable Interrupt Mask Pointer 17. See P6IMSKP.
Programmable Interrupt Mask Pointer 18. See P6IMSKP.
, which stores return addresses and top-of-loop
PCSTK
A-10, the address buses can handle 32-bit addresses,
Registers Reference
couples with the Program
PC
only).
Ureg
A-33