Spi Transfer Formats - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

SPI Transfer Formats

Table 10-2. DMA Chaining Sequence
Address
CPSPI
CPSPI – 1
CPSPI – 2
CPSPI – 3
SPI Transfer Formats
The ADSP-2126x SPI supports four different combinations of serial clock
phases and polarity. The application code can select any of these combina-
tions using the
Figure 10-6 on page 10-27
where starts toggling in the middle of the data transfer,
SPICLK
= 1. Figure 10-7 on page 10-28
MSBF
= 1. Each diagram shows two waveforms for
CPHASE
= 0 and the other for
CLKPL
master or slave timing diagrams since the
directly connected between the master and the slave. The
output from the slave (slave transmission), and the
put from the master (master transmission).
The signal is generated by the master, and the
SPICLK
resents the slave device select input to the processor from the SPI master.
The diagrams represent 8-bit transfers (
Any combination of the
For example, a 16-bit transfer with the LSB first is one possible
configuration.
The clock polarity and the clock phase should be identical for the master
device and slave devices involved in the communication link. The transfer
10-26
Register
DMA Start Address
DMA Address Modifier
DMA Word Count
DMA Next TCB
and
CLKPL CPHASE
shows the transfer format when
CLKPL
and
WL MSBF
ADSP-2126x SHARC Processor Hardware Reference
Description
Address in Memory
Address increment
Number of words to transfer
Pointer to address of next TCB
bits in the
SPICTL
shows the transfer format when
= 1. The diagrams may be interpreted as
,
SPICLK MISO
MOSI
= 0) with MSB first (
WL
bits of the
SPICTL
register.
= 0
CPHASE
= 0, and
WL
—one for
SPICLK
, and pins are
MOSI
signal is the
MISO
signal is the out-
signal rep-
SPIDS
= 1).
MSBF
register is allowed.