Spiclk Timing; Spi Slave Select Outputs (Spids0-3) - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

The signal is used to shift out the data driven onto the
SPICLK
and shift in the data driven onto the
out on one edge of the clock (referred to as the active edge) and sampled
on the opposite edge of the clock (referred to as the sampling edge). Clock
polarity and clock phase relative to data are programmable via bit 11
( ) and bit 10 (
CLKPL

SPICLK Timing

When the processor is configured as an SPI-Slave, the SPI-master must
drive an
SPICLK
parameters, please refer to the appropriate ADSP-2126x data sheet.
The lead time (T1), the
SPIDS
transfer delay time (T3) must always be greater than or equal to one-half
the period. The minimum time between successive word transfers
SPICLK
(T4) is two
SPICLK
active edge of
SPICLK
next word. This calculation is independent from the configuration of the
SPI ( ,
CPHASE SPIMS
SPI CLK
CPHASE =0
SPIDS
TO SLAVE
Figure 10-3. SPICLK Timing

SPI Slave Select Outputs (SPIDS0-3)

When =0, the SPI port hardware controls the device-select signal
CPHASE
automatically (determined by
ADSP-2126x SHARC Processor Hardware Reference
) in the
CPHASE
signal that conforms with
SPIDS
periods. This time period is measured from the last
of one word to the first active edge of
, and so on).
T1 T2
T3
T4
DSxEN
Serial Peripheral Interface Port
lines. The data is always shifted
MOSI
control register.
SPICTL
Figure 10-3. For exact timing
lag time (T2), and the sequential
bits in ). Setting
SPIFLG
lines
MISO
of the
SPICLK
=1
CPHASE
10-5