14 Peripheral Timer; Timer Architecture - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

14 PERIPHERAL TIMER

In addition to the internal core timer, the ADSP-2126x contains three
identical 32-bit timers that can be used to interface with external devices.
Each timer can be individually configured in any of three modes:
• "Pulse Width Modulation Mode (PWM_OUT)" on page 14-7
• "Pulse Width Count and Capture Mode (WDTH_CAP)" on
page 14-10
• "Pulse Width Count and Capture Mode (WDTH_CAP)" on
page 14-10

Timer Architecture

Each timer has one dedicated bidirectional chip signal,
timer signals are connected to the 20 Digital Audio Interface (DAI) pins
through the Signal Routing Unit (SRU). The timer signal functions as an
output signal in
modes. To provide these functions, each timer has four, 32-bit
EXT_CLK
registers. The registers for each timer are:
• Timer x Configuration (
• Timer x Word Count (
• Timer x Word Period (
• Timer x Word Pulse Width (
ADSP-2126x SHARC Processor Hardware Reference
mode and as an input signal in
PWM_OUT
TMxCTL
TMxCNT
TMxPRD
) register
) register
) register
) register
TMxW
. The three
TIMERx
and
WDTH_CAP
14-1