Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 696

I/O Processor Registers
SPCTL1 (0xc01)
SPCTL3 (0x401)
SPCTL5 (0x801)
RXS_A
Data Buffer Channel A Status
11=Full 10=Partially Full 00=Empty
ROVF_A
Channel A Underflow Status (sticky)
RXS_B
Data Buffer Channel B Status
11=Full 10=Partially Full 00=Empty
ROVF_B
Channel B Underflow Status (sticky)
Reserved
BHD
Buffer Hang Disable
1=Ignore Core Hang
0=Core Stall when TXn full or RXn Empty
Reserved
SCHEN_B
Receive DMA Channel B Chaining Enable
1=Enable
0=Disable
Reserved
IMFS
Internally Generated Multichannel
Frame Sync
1=Internal Frame Sync
0=External Frame Sync
Reserved
CKRE
Active Clock Edge for Data and Frame
Sync Sampling
1=Rising Edge
0=Falling Edge
OPMODE
SPORT Operation Mode
1=I2S or Left-justified Sample pair Mode
0=DSP Serial Mode/Multichannel Mode
ICLK
Internally Generated Clock
1=Internal Clock
0=External Clock
Figure A-22. SPCTLx Receive Control Bits – Multichannel Mode
A-74
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
0 0 0 0 0 0 0 0
ADSP-2126x SHARC Processor Hardware Reference
0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
LMFS
Active Low MC
Transmit Data valid
1=Active low FS
0=Active High FS
Reserved
SDEN_A
Receive DMA
Channel A Enable
1=Enable
0=Disable
SCHEN_A
Receive DMA Channel A
Chaining Enable
1=Enable
0=Disable
SDEN_B
Receive DMA
Channel B Enable
1=Enable
0=Disable
Reserved
DTYPE
Data Type
00=Right Justify,
Fill MSB with 0's
01=Right Justify,
Sign extend MSB
10=Compand µ-law
11=Compand A-law
LSBF
Serial Word Bit Order
1=LSB First
0=MSB First
SLEN
Serial Word Length-1
PACK
16/32 Packing
1=Packing
0=No Packing