Extended-Precision Normal Word Addressing Of Single-Data - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Internal Memory Access Listings
Extended-Precision Normal Word Addressing of
Single-Data
Figure 5-19 on page 5-49
extended-precision normal word addressed access. For extended-precision
normal word addressing, the processor treats each data bus as a 40-bit
extended-precision normal word lane. The 40-bit value for the
extended-precision normal word access is transferred using the most sig-
nificant 40 bits of the PM or DM data bus. The processor drives the lower
24 bits of the data buses with zeros.
In Figure 5-19, the access targets a
operation; extended-precision normal word single-data access operate the
same in SISD or SIMD mode. This instruction accesses
tax that targets register
using the syntax

Extended precision can't be supported in SIMD mode since the
both PM and DM data buses are limited to 64-bits but would
require 80-bits.
5-48
displays a possible single-data, 40-bit
in . The example targets a
RX PEx
.
SX
ADSP-2126x SHARC Processor Hardware Reference
register in a SISD or SIMD mode
PEx
with syn-
WORD X0
register when
PEy