Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 703

SPMCTL23
(0x404)
DMACHS3B
SPORT3 Channel B Status
DMA Chaining Status
DMACHS3A
SPORT3 Channel A Status
DMA Chaining Status
DMACHS2B
SPORT2 Channel B Status
DMA Chaining Status
DMACHS2A
SPORT2 Channel A Status
DMA Chaining Status
DMAS3B
SPORT3 Channel B Status
DMA Status
DMAS3A
SPORT3 Channel A Status
DMA Status
15 14 13 12 11 10
Reserved
SPL
SPORT Loopback
SPORT0 A to SPORT1 A Only
SPORT0 B to SPORT1 B Only
NCH
Number of Channels – 1
Figure A-25. SPMCTL23 Registers – Multichannel Mode
ADSP-2126x SHARC Processor Hardware Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0
9 8
0 0 0 0 0 0 0 0
Registers Reference
0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
CHNL
Current Channel Status
(read-only)
MCEB
Multichannel Enable
B Channels
1=Enable
0=Disable
DMAS2A
SPORT2 Channel
A Status
DMA Status
DMAS2B
SPORT2 Channel
B Status
DMA Status
MCEA
Multichannel Enable
A Channels
1=Enable
0=Disable
MFDx
Multichannel Frame
Delay
A-81