Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 212

Buses
The register-to-internal memory transfers over the DM or PM data bus
PX
are either 48-bit transfers for the combined
31-0 of the bus) for
Instruction Examples
PX = DM (0xC0000) (LW);
DM and PM Data Bus Transfer (not LW)
48 bits
63 31
48 bits
63 31
PX2
Combined PX
Figure 5-4. PX, PX1, PX2 Register-to-Memory Transfers on DM (LW) or
PM (LW) Data Bus
Figure 5-5 shows that during a transfer between
memory, the bus transfers the lower 32 bits of the register.
During a transfer between the combined
the bus transfers the upper 48 bits of

The status of the memory block's Internal Memory Data Width
( ) setting does not effect this default transfer size for
IMDWX
internal memory.
All transfers between the
memory) and any I/O processor register are 32-bit transfers (least signifi-
cant 32 bits of
5-8
or . Figure 5-5
PX1 PX2
0x0
8 7 0
0x0
8 7 0
PX1
register (or any other internal register or
PX
).
PX
ADSP-2126x SHARC Processor Hardware Reference
or 32-bit transfers (on bits
PX
shows these transfers.
PM(I7,M7) = PX1;
DM or PM Data Bus Transfer
0x0
63 31
31
PX1 or PX2
or
PX1 PX2
register and internal memory,
PX
and zero-fills the lower 8 bits.
PX
32 bits
0
32 bits
0
and internal
to
PX