Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 47

Introduction
sequencer supply addresses for memory accesses. Together the sequencer
and data address generators allow computational operations to execute
with maximum efficiency since the computation units can be devoted
exclusively to processing data. With its instruction cache, the
ADSP-2126x can simultaneously fetch an instruction from the cache and
access two data operands from memory. The DAGs also provide built-in
support for zero-overhead circular buffering.
Program Sequencer. The program sequencer supplies instruction
addresses to program memory. It controls loop iterations and evaluates
conditional instructions. With an internal loop counter and loop stack,
the ADSP-2126x executes looped code with zero overhead. No explicit
jump instructions are required to loop or to decrement and test the
counter. To achieve a high execution rate while maintaining a simple pro-
gramming model, the DSP employs a three stage pipeline to process
instructions—fetch, decode, and execute cycles.
Data Address Generators. The DAGs provide memory addresses when
data is transferred between memory and registers. Dual data address gen-
erators enable the processor to output simultaneous addresses for two
operand reads or writes. DAG1 supplies 32-bit addresses for accesses using
the DM bus. DAG2 supplies 32-bit addresses for memory accesses over
the PM bus.
Each DAG keeps track of up to eight address pointers, eight address mod-
ifiers, and for circular buffering eight base-address registers and eight
buffer-length registers. A pointer used for indirect addressing can be mod-
ified by a value in a specified register, either before (pre-modify) or after
(post-modify) the access. A length value may be associated with each
pointer to perform automatic modulo addressing for circular data buffers.
The circular buffers can be located at arbitrary boundaries in memory.
Each DAG register has a secondary register that can be activated for fast
context switching.
Circular buffers allow efficient implementation of delay lines and other
data structures required in digital signal processing They are also
ADSP-2126x SHARC Processor Hardware Reference 1-7