Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 593

Table 15-2. ADSP-2126x Processor Pin Multiplexing Scheme
External Pin
1
FLGn
AD[15:0]
6
DAI_P[20:1]
CLKOUT
1 n = 0, 1, 2, 3.
2 For n = 3 function is FLG3 or TIMEXP, not
3 These pins are used at boot time as device selects during SPI Master booting.
4 Setting PPFLGS = 1 and IDP_PP_SELECT = 1 at the same time is illegal.
5 When PPFLGS = 1, the FLG pins toggle then alternate functions. For example
TIMEXP.
6 For complete information on the operation of these pins, see
page 12-1.
7 For complete information on the operation of these pins, see
isters (SRU_CLKx, Group A)" on page
ADSP-2126x SHARC Processor Hardware Reference
Function Type
I = input
O = output
FLGn I/O
I
IRQn 2
3 O
SPI Device Select
AD[15:0] I/O
PDAP I
FLG[15:0] I/O
PDAP I
FLG[15:10] I/O
Other I/O
CLKOUT O
O
RESETOUT
A-114.
Control
0 = cleared
1 = set
x = do not care
PPFLGS = 0
SPIFLG[n] = 0 and SPIMS=0
IRQxEN = 0
PPFLGS=0
SPIFLG[n] = 0 and SPIMS = 0
IRQxEN = 1
PPFLGS=0
SPIFLG[n] = 1 and SPIMS = 1
IRQxEN = 0
4
PPFLGS = 0
IDP_PP_SELECT = 0
PPFLGS = 0
IDP_PP_SELECT = 1
5
PPFLGS = 1
IDP_PP_SELECT = 0
IDP_PP_SELECT = 0
7
Note
6
Note
PMCTL [12] = 1 (for debug only)
PMCTL [12] = 0
.
IRQ3
"Digital Audio Interface" on
"Clock Routing Control Reg-
System Design
and
IRQx
15-3