Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 610

Booting
The ADSP-2126x supports three booting modes—EPROM, SPI master
and SPI slave. Each of these modes uses the following general procedure:
1. At reset, the ADSP-2126x is hardwired to load two hundred
fifty-six 32-bit instruction words via a DMA starting at location
0x80000. In this chapter, these instructions are referred to as the
boot kernel or loader kernel.
2. The DMA completes and the interrupt associated with the periph-
eral that the processor is booting from is activated. The processor
jumps to the applicable interrupt vector location (0x80030 for SPI
and 0x80050 for the parallel port) and executes the code located
there. (Typically, the first instruction at the interrupt vector is a
Return From Interrupt (RTI) instruction.)
3. The loader kernel executes a series of Direct Memory Accesses
(DMAs) to import the rest of the application, overwriting itself
with the applications' Interrupt Vector Table (IVT).
4. After executing the kernel, the processor returns to location
0x80005 where normal program execution begins.
To support this process, a 256-word loader kernel and loader (which con-
verts executables into boot-loader images) are supplied with the CrossCore
or VisualDSP++ development tools for both SPI and parallel port booting.
For more information on the loader, see the tools documentation.
The boot source is determined by strapping the two
either logic low or logic high. These settings are shown in
15-20 ADSP-2126x SHARC Processor Hardware Reference
pins to
BOOTCFGx
Table 15-6.