Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 748

I/O Processor Registers
Table A-36. Group C Sources – Frame Sync (Cont'd)
Selection Code
11100 (0x1C)
11101 (0x1D)
11110 (0x1E)
11111 (0x1F)
Pin Signal Assignment Registers
(SRU_PINx, Group D)
Each physical pin (connected to a bonded pad) can be routed via the SRU
to any of the inputs or outputs of the DAI peripherals, based on the 6-bit
values listed in
control the pins in other ways. The pin signal assignments are shown in
the following figures:
•
SRU_PIN0
•
SRU_PIN1
•
SRU_PIN2
•
SRU_PIN3
A-126
Source Signal
PCG_FSA_O
PCG_FSB_O
LOW
HIGH
Table A-37. The SRU can also be used to route signals that
, described in Figure A-46
, described in Figure A-47
, described in Figure A-48
, described in Figure A-49
ADSP-2126x SHARC Processor Hardware Reference
Description
Select Precision Frame Sync A Output as
the source
Select Precision Frame Sync B Output as
the source
Select Logic Level Low (0) as the source
Select Logic Level High (1) as the source