SPORTX_CLK
FRAMED
DATA
UNFRAMED
DATA
Figure 9-6. Framed Versus Unframed Data
Internal Versus External Frame Syncs
Both transmit and receive frame syncs can be generated internally or input
from an external source. The
mines the frame sync source.
When
is set (=1), the corresponding frame sync signal is generated
IFS
internally by the processor, and the
frequency of the frame sync signal is determined by the value of the frame
sync divisor (
FSDIV
When
is cleared (=0), the corresponding frame sync signal is accepted
IFS
as an input on the
registers are ignored.
DIVx
All frame sync options are available whether the signal is generated inter-
nally or externally.
ADSP-2126x SHARC Processor Hardware Reference
B
B
B
B
3
2
1
0
B
B
B
B
3
2
1
0
bit of the
IFS
) in the
register. Refer to
DIVx
signals, and the frame sync divisors in the
SPORTx_FS
B
B
3
2
B
B
B
B
3
2
1
0
Control register deter-
SPCTLx
signal is an output. The
SPORTx_FS
Figure 9-8 on page
Serial Ports
B
B
1
0
B
B
B
3
2
1
9-63.
9-35
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