Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 130

Conditional Sequencing
( and
ASTATx ASTATy
and the loop counter. For more information on arithmetic status, see
"Using Computational Status" on page
ditional execution is effected by the arithmetic status of both processing
elements. For information on conditional sequencing in SIMD mode, see
"Summary" on page
Each condition that the DSP evaluates has an assembler mnemonic. The
condition mnemonics for conditional instructions appear in
For most conditions, the sequencer can test both true and false states. For
example, the sequencer can evaluate ALU equal-to-zero (
not-equal-to-zero (
To branch conditionally based on the value of a register, a program can
use the Test Flag (
instruction. The
instruction, which can test the contents of any of the DSP's system regis-
ters, including
3-18
), the mode control 1 register (
3-61.
).
NZ
) condition generated from a Bit Test Flag (
TF
flag is set or cleared as a result of a
TF
and .
STKYx STKYy
ADSP-2126x SHARC Processor Hardware Reference
), the flag inputs,
MODE1
2-16. When in SIMD mode, con-
EQ
BIT TST
Table 3-6.
) and ALU
)
BTF
or
BIT XOR