Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 823

IDP_PDAP_RESET bit, 11-7,
IDP_PORT_SELECT bit, 11-7, 11-19,
A-156
IDP_PORT_SELECT bits,
IDP_Px_PPMASK bits, 11-17,
IDP_Pxx_PPMASK bits,
IDP_SMODEx bits, 11-4, 11-16,
IEEE 1149.1 JTAG standard,
IEEE 754/854 floating-point data format,
2-3, 2-12
IEEE floating-point number conversion,
2-14
IFS bit, 9-55
IFS or IRFS bit, A-77
IICD bit, 5-21
IICD (illegal input condition interrupt) bit,
A-28
IIMDWx bits, 5-8
IIPP register, 8-16, A-112
IIRAE bit, 5-21, 5-28
IIRAE (illegal IOP register access enable)
bit, A-9
IIRAE (illegal IOP register access
enable) bit, A-9
IIRA (illegal IOP register access) bit,
IISPI register, 10-39, A-106
IISPx registers, 7-24, 7-26,
IIVT bit, 5-27
IIVT (internal interrupt vector table
enable) bit, 5-18
illegal input condition detected (IICD) bit,
5-21, A-28
illegal IOP register access (IIRA) bit,
illegal I/O processor register access enable
(IIRAE) bit, 5-21, 5-28,
IMASK control register,
IMASK (interrupt mask) register,
IMASKP (interrupt mask pointer) register,
A-26
ADSP-2126x SHARC Processor Hardware Reference
A-157
11-17
11-19
11-8
11-19
G-6
A-19
A-90
A-19
A-9
3-64
A-25
IMDWx (internal memory data width)
bits, 5-12, 5-19, 5-22,
implicit operations, 5-20
broadcast load, 4-6
complementary registers,
long word (LW) accesses,
neighbor registers, 5-24
SIMD mode, 2-47
IMPP register, 8-16, 15-22,
IMSPI register, 10-39,
IMSPI (serial peripheral interface address
modify) register, 10-46,
IMSPx registers, 7-24, 7-26,
INCLUDE directory, 9-44
increment instruction,
INDATA interrupt enable
(EEMUINENS) bit, A-57,
index (Ix) registers, 4-2, 4-16,
index See Ix registers
indirect addressing, 1-7
indirect branch, 3-12, G-5
inexact flags, G-5
infinity, round-to, 2-13
input data port buffer See IDP_FIFO
register
input data port control buffer See
IDP_CTL register
Input Data Port Control (IDP_CTL)
register, A-149
input data port control registers,
See also IDP_CTL register
Input Data Port FIFO (IDP_FIFO)
register, A-150
input data port (IDP), 11-1,
input/output (I/O) bus,
input setup and hold time,
input signal conditioning,
input slave select enable See ISSEN bit
input synchronization delay,
Index
5-27
2-47
5-23
A-112
A-106
10-48
A-90
2-17
A-61
A-37
A-148
12-2
1-2
15-4
15-14
15-12
I-13