Sport Receive Compand Registers (Mrxccsy - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Each bit, 31–0, set (= 1) in one of the four
an active receive channel, 127–0, on a Multichannel mode serial port.
When the
MRxCSx
word in that channel's position of the data stream and loads the word into
the buffer. When a channel's bit in the
RXSPx
0), the serial port ignores any input during the channel's receive time slot.

SPORT Receive Compand Registers (MRxCCSy)

These addresses for the
MR1CCS0 – 0xC11
MR1CCS2 – 0xC13
MR3CCS0 – 0x411
MR3CCS2 – 0x413
MR5CCS0 – 0x811
MR5CCS2 – 0x813
The reset value for these registers is undefined.
Each bit, 31–0, set (= 1) in the
panded receive channel, 127–0, on a Multichannel mode serial port.
When one of the four
nel, the serial port applies the companding from the serial port's
selection to the received word in that channel's position of the data
stream. When a channel's bit in the
serial port does not compand the input during the channel's receive time
slot.
ADSP-2126x SHARC Processor Hardware Reference
register activates a channel, the SPORT receives the
registers are:
MRxCCSy
MR1CCS1 – 0xC12
MR1CCS3 – 0xC14
MR3CCS1 – 0x412
MR3CCS3 – 0x414
MR5CCS1 – 0x812
MR5CCS3 – 0x814
MRxCCSy
registers activate companding for a chan-
MRxCCSy
MRxCCSy
Registers Reference
registers corresponds to
MRCSx
register is cleared (=
MRxCSx
registers corresponds to an com-
registers are cleared (= 0), the
DTYPE
A-89