Nesting Interrupts - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Interrupts and Sequencing

Nesting Interrupts

The sequencer supports interrupt nesting—responding to another inter-
rupt while a previous interrupt is being serviced. Bits in the
and registers control interrupt nesting as described below.
LIRPTL
• Interrupt Nesting enable.
the DSP to enable (if 1) or disable (if 0) interrupt nesting.
• Interrupt Mask Pointer.
in priority order and provide a temporary interrupt mask for each
nesting level.
• SPI Port DMA Transmit or Receive Interrupt Mask Pointer.
LIRPTL
receive DMA interrupt. It provides a temporary interrupt mask.
• General-Purpose IOP Timer Interrupt Mask Pointer.
24 and 28 (
general purpose IOP timer 1 and timer 2 interrupts, respectively.
They provide a temporary interrupt mask.
• Serial Port Interrupt Mask Pointer.
(
SPxMSKP
and
SP4
• DAI Low Priority Interrupt Mask Pointer.
(
DAILIMSKP
vides a temporary interrupt mask.
When interrupt nesting is enabled, a higher priority interrupt can inter-
rupt a lower priority interrupt's service routine. Lower priority interrupts
are latched as they occur, but the DSP processes them according to their
priority after the nested routines finish.
3-58
IMASKP
Bit 29 (
SPILIMSKP
and
GPTMR1MSKP
). These bits are for the serial port interrupts (
). They provide a temporary interrupt mask.
). This bit is for the DAI low priority interrupt. It pro-
ADSP-2126x SHARC Processor Hardware Reference
Bit 11 (
MODE1 NESTM
bits. These bits list the interrupts
). This bit is for the SPI port transmit or
). These bits are for the
GPTMR2MSKP
LIRPTL
,
MODE1 IMASKP
). This bit directs
LIRPTL
Bits 22-20
,
SP0 SP2
Bit 26
LIRPTL
,
Bits
,