Pulse Width Modulation Mode (Pwm_Out) - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Any of the timers can be used to implement a watchdog functionality that
can be controlled by either an internal or an external clock source.
For software to service the watchdog, the program must reset the timer
value by disabling and then re-enabling the timer. Servicing the watchdog
periodically prevents the Count register from reaching the period value
and prevents the timer interrupt from being generated. When the timer
reaches the period value and generates the interrupt, reset the DSP within
the corresponding watchdog's ISR.

Pulse Width Modulation Mode (PWM_OUT)

In mode, the timer supports on-the-fly updates of period and
PWM_OUT
width values of the PWM waveform. The period and width values can be
updated once every PWM waveform cycle, either within or across PWM
cycle boundaries.
To enable
PWM_OUT
figuration (
TMxCTL
an output with its polarity determined by
• If
PULSE
ated at the
• If
PULSE
erated at the
The timer is actively driven as long as the
Figure 14-3 shows a flow diagram for
becomes enabled, the timer checks the period and width values for plausi-
bility (independent of the value set with the
to count when any of the following conditions are true:
ADSP-2126x SHARC Processor Hardware Reference
mode, set the
TIMODE1–0
) register. This configures the timer's
is set (= 1), an active high width pulse waveform is gener-
signal.
TIMERx
is cleared (= 0), an active low width pulse waveform is gen-
signal.
TIMERx
Peripheral Timer
bits to 01 in the timer's Con-
TIMERx
as follows:
PULSE
field remains 01.
TIMODE
mode. When the timer
PWM_OUT
bit) and does not start
PRDCNT
signal as
14-7