Conditioning Input Signals; Input Pin Hysteresis - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Conditioning Input Signals

counts up to 4096
high. The delay circuit is activated at the same time the PLL is taken out
of reset.
The advantage of the delayed core reset is that the PLL can be reset any
number of times without having to power-down the system. If there is a
brown-out situation, the watchdog circuit only has to control the
Conditioning Input Signals
The processor is a CMOS device. It has input conditioning circuits which
simplify system design by filtering or latching input signals to reduce sus-
ceptibility to glitches or reflections.
The following sections describe why these circuits are needed and their
effect on input signals.
A typical CMOS input consists of an inverter with specific N and P device
sizes that cause a switching point of approximately 1.4 V. This level is
selected to be the midpoint of the standard TTL interface specification of
V = 0.8 V and V
IL
response to input signals and external glitches wider than 1 ns. Filter cir-
cuits and hysteresis are added after the input inverter on some processor
inputs, as described in the following sections.

Input Pin Hysteresis

Hysteresis (shown in
Hysteresis causes the switching point of the input inverter to be slightly
above 1.4 V (VT) for a rising edge (VT+) and slightly below 1.4 V for a
falling edge (VT–). The value of the hysteresis is approximately ± 100 mV.
The hysteresis is intended to prevent multiple triggering of signals that are
allowed to rise slowly, as might be expected for example on a reset line
with a delay implemented by an RC input circuit. Hysteresis is not used to
15-14
cycles after
CLKIN
= 2.0 V. This input inverter, unfortunately, has a fast
IH
Figure 15-4) is used on all SHARC input signals.
ADSP-2126x SHARC Processor Hardware Reference
is transitioned from low to
RESET
.
RESET