Master Boot - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Booting

Master Boot

In Master Boot mode, the ADSP-2126x initiates the booting operation
by:
1. Activating the
active low state.
2. Writing the read command 0x03 and address 0x00 to the slave
device as shown in
Master Boot mode is used when the processor is booting from an SPI
compatible serial PROM, serial FLASH, or slave host processor. The spe-
cifics of booting from these devices are discussed individually. On reset,
the interface starts up in Master mode performing a three hundred
eighty-four 32-bit word DMA transfer.
SPI master booting uses the default bit settings shown in
Table 15-11. SPI Master Boot Mode Bit Settings
Bit Setting
SPIEN Set (= 1)
SPIMS Set (= 1)
MSBF Cleared (= 0)
WL 10
DMISO Cleared (= 0)
SENDZ Set (= 1)
SPIRCV Set (= 1)
CLKPL Set (= 1)
CPHASE Set (= 1)
15-30
signal and asserting the
SPICLK
Figure 15-8.
Comment
SPI Enabled
Master device
LSB first
32-bit SPI Receive Shift register word length
MISO enabled
Send zeros
Receive DMA enabled
Active low SPI clock
Toggle SPICLK at the beginning of the first bit
ADSP-2126x SHARC Processor Hardware Reference
signal to the
FLG0
Table 15-11.