Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 784

I/O Processor Registers
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAI_STAT (0x24B8)
0
IDP_FIFOSZ
Number of Valid Data in IDP FIFO
Reserved
IDP_FIFO_OVER
Overflow (Sticky) Bit
IDP_DMA7_STAT
IDP_DMA6_STAT
15 14 13 12 11 10
Reserved
SRU_EXTMISCB5
SRU_EXTMISCB4
SRU_EXTMISCB3
SRU_EXTMISCB2
SRU_EXTMISCB1
SRU_EXTMISCB0
Figure A-70. DAI_STAT Register
Table A-51. DAI_STAT Register Bit Descriptions
Bits Name
11–0 SRU_EXTMISCyx
16–12 Reserved
24–17 IDP_DMAx_STAT
25 IDP_FIFO_OVER
27–26 Reserved
31–28 IDP_FIFOSZ
A-162
0 0 0 0 0 0 0
9 8
0 0 0 0 0 0 0 0
Description
ADSP-2126x SHARC Processor Hardware Reference
0 0 0 0 0 0 0
7 6 5 4 3 2 1
0 0 0 0 0 0 0
Miscellaneous Input A/B Signals. Indicate the status
of the MISCxy_I signals.
Input Data Port DMA Status.
1 = DMA is active
0 = DMA is not active
IDP_FIFO Overflow Status. This (sticky) bit provides
IDP FIFO overflow status information.
1 = Overflow has occurred
0 = No overflow
Number of samples in FIFO
0
IDP_DMA0_STAT
DMA Active Status for
IDP Channel 0
IDP_DMA1_STAT
IDP_DMA2_STAT
IDP_DMA3_STAT
IDP_DMA4_STAT
IDP_DMA5_STAT
0
0
SRU_EXTMISCB0
Miscellaneous Input A0
SRU_EXTMISCA1
SRU_EXTMISCA2
SRU_EXTMISCA3
SRU_EXTMISCA4
SRU_EXTMISCA5