Interrupt Vector - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

B INTERRUPT VECTOR
ADDRESSES
Table B-2 shows all the ADSP-2126x processor interrupts, listed accord-
ing to their bit position in the IRPTL, LIRPTL, and IMASK registers. For
more information, see
"Interrupt Register (LIRPTL)" on page
ter (IMASK)" on page
vector. Each vector is separated by four memory locations. The addresses
in the vector table represent offsets from a base address. For an Interrupt
Vector Table in internal RAM, the base address is 0x8 0000 and for inter-
nal ROM, the base address is 0xA 0000. These are 48-bit addresses.
Table B-1. Interrupt Vector Table Base Address
1
Address
0x0008 0000
0x000A 0000
1 These are 48-bit addresses.
The interrupt name column in
interrupt as they are defined by the definitions file (def2126x.h) that
comes with the software development tools.

SPI has only one interrupt for both transmit and receive.

Each serial port (SPORT) has only one interrupt for both transmit
and receive.
ADSP-2126x SHARC Processor Core Manual
"Interrupt Latch Register (IRPTL)" on page
A-25. Also shown is the address of the interrupt
Description
Internal RAM
Internal ROM
Table B-2
A-30, and "Interrupt Mask Regis-
lists a mnemonic name for each
A-25,
B-1