Table of Contents
Advertisement
SRU_CLK0 (0x2430)
Reserved
SPORT5_CLK_I
Serial Port 5 Clock Input
15 14 13 12 11 10
0
SPORT2_CLK_I
Serial Port 2 Clock Input
SPORT1_CLK_I
Serial Port 1 Clock Input
Figure A-34. SRU_CLK0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SRU_CLK1 (0x2432)
Reserved
IDP2_CLK_I
Input Data Port 2 Clock Input
15 14 13 12 11 10
0
Figure A-35. SRU_CLK1 Register
ADSP-2126x SHARC Processor Hardware Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
1
0
0
1
0
1
9
8
0
1
1
0
0
0
0
0
0
1
1
1
1
0
1
9
8
1
1
1
1
0
1
1
Registers Reference
0
0
1
0
0
1
1
7
6
5
4
3
2
1
0
1
1
0
0
0
0
1
0
1
1
1
0
1
1
1
7
6
5
4
3
2
1
0
1
1
0
1
1
1
1
0
0
SPORT3_CLK_I
Serial Port 3 Clock Input
SPORT4_CLK_I
Serial Port 4 Clock Input
SPORT0_CLK_I
Serial Port 0 Clock Input
1
IDP0_CLK_I
Input Data Port 2 Clock Input
IDP1_CLK_I
Input Data Port 2 Clock Input
Reserved
A-115
Advertisement
Table of Contents
Need help?
Do you have a question about the ADSP-21261 SHARC and is the answer not in the manual?
Questions and answers