Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 413

The bit field specifies how many times the processor's internal
CLKDIV
clock ( ) is divided to generate the transmit and receive clocks. The
CCLK
frame sync (
SPORTx_FS
nals are configured as receivers. Likewise, the frame sync
considered a transmit frame sync if the data signals are configured as
transmitters. The divisor is a 15-bit value, allowing a wide range of serial
clock rates.
Use the following equation to calculate the serial clock frequency:
The maximum serial clock frequency is equal to one-quarter the proces-
sor's internal clock (
zero. Use the following equation to determine the value of
the frequency and desired serial clock frequency:
CCLK
DIV0 (0xC02)
DIV1 (0xC03)
DIV2 (0x402)
DIV3 (0x403)
DIV4 (0x802)
DIV5 (0x803)
CLKDIV
Clock Divisor
Figure 9-8. DIVx Register
The bit field
FSDIV
counted before a frame sync pulse is generated. In this way, a frame sync
ADSP-2126x SHARC Processor Hardware Reference
) is considered a receive frame sync if the data sig-
= f
f
SPORTx_CLK
4(CLKDIV+1)
) frequency, which occurs when
CCLK
CLKDIV =
4(f
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
0 0 0 0 0 0 0 0
specifies how many transmit or receive clock cycles are
CCLK
f
CCLK
– 1
)
SPORTx_CLK
0 0 0 0 0 0 0 0
7 6 5 4 3 2 1
0 0 0 0 0 0 0
Serial Ports
is
SPORTx_FS
is set to
CLKDIV
, given
CLKDIV
0
FSDIV
Frame Sync Divis
0
0
Reserved
9-63