Texas Instruments F28M35H52C-Q1 Manuals
Manuals and User Guides for Texas Instruments F28M35H52C-Q1. We have 1 Texas Instruments F28M35H52C-Q1 manual available for free PDF download: Technical Reference Manual
Texas Instruments F28M35H52C-Q1 Technical Reference Manual (1655 pages)
Brand: Texas Instruments
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Category: Microcontrollers
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Size: 11 MB
Table of Contents
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Preface78
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WIR Mode92
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PIE Vector Table110
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Safety Features119
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Nmiwds124
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Watchdog Timers124
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Clock Control125
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Power Control125
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Clock Sources126
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Plls126
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CPU-Timers136
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Low Power Modes140
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Security Levels145
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Zone ECSL Status155
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Μcrc Module155
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CRC Polynomials156
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Msgrams157
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CSMKEY1 Register264
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CSMKEY2 Register264
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CSMKEY3 Register264
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CSMCR Register265
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Μcrcres Register269
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Block Diagram299
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GPTM Features299
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Timer Modes301
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DMA Operation305
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16-Bit PWM Mode308
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Register Map308
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Block Diagram325
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Introduction325
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Register Map326
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Introduction337
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Digital I/O Pads342
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Register Map346
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Introduction369
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Sampling Period381
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Gpioa Mux386
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Gpiob Mux387
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Gpioc Mux388
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Analog MUX389
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Gpioe Mux389
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RAM Control426
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Flash Cache Mode498
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Device Boot Flow540
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SPI Loader604
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Random Read609
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Sequential Read609
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Event Filtering705
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Pwm1 ≠ F709
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Pwm1 )712
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Pwm2 Pwm1712
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Pwm1) )713
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Pwm2 Pwm1713
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Pwm2 Pwm1)726
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EQEP Memory Map824
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16-Bit Read857
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16-Bit Write857
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32-Bit Read858
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ADC Trigger858
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ADC Interrupt859
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ADC Registers872
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Comparator902
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Descriptions942
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Descriptions943
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SPI Registers948
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SPI Operation949
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SPI Interrupts951
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Loopback Modes962
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Level Is High.)975
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Architecture982
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SCI-A Registers982
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SCI-B Registers982
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SCI Registers994
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SCIA Registers994
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SCIB Registers994
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Features1009
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Functional Overview1009
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Clock Generation1010
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Data Validity1011
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Operating Modes1012
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Serial Data Formats1013
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NACK Bit Generation1015
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Arbitration1016
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I2C FIFO Interrupts1018
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I2C Module Registers1019
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Overview1037
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Mcbsp Pins/Signals1038
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Mcbsp Operation1039
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Companding Processes1041
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Clocking1042
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Serial Words1042
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Frame Frequency1044
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Frame Phases1044
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Mcbsp Reception1046
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Mcbsp Transmission1048
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Block Diagram1050
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Types of Errors1056
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2-Partition Mode1065
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Using Two Partitions1065
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SPI Protocol1071
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Clock Stop Mode1072
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Mcbsp Emulation Mode1114
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Mcbsp Registers1118
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Register Summary1119
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Pin Configuration1140
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Interrupt Generation1144
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Error Flags1145
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Mcbsp Mode Selection1146
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Block Diagram1149
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Overview1149
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Μdma Block Diagram1150
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Channel Assignments1151
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Arbitration Size1152
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Priority1152
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Request Types1152
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Request Type Support1153
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Transfer Modes1154
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Peripheral Interface1163
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Software Request1163
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Register Map1169
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Introduction1191
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EPI Block Diagram1192
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Non-Blocking Reads1193
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DMA Operation1194
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SDRAM Mode1195
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Bus Interface Speed1197
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Normal Read Cycle1197
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Write Cycle1198
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Control Pins1199
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Host Bus Mode1199
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SDRAM Write Cycle1199
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Irdy Access Stalls1209
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Host Bus Operation1212
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Alehigh1213
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General-Purpose Mode1215
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Two-Entry FIFO1215
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C28X Access to EPI1223
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Memory Protection1224
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Register Map1225
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CEPIRTWCFG Register1276
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CEPIRTWCNT Register1276
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CEPIRTWPRD Register1277
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CEPISTATUS Register1277
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MEMPROT Register1277
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Block Diagram1280
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Introduction1280
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USB Block Diagram1280
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Operation as a Host1285
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OTG Mode1288
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Actual Bytes Read1290
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DMA Operation1290
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Pin Configuration1291
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Register Map1292
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Usbrxcsrh[15])1348
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EMAC Block Diagram1381
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Ethernet MAC1381
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Introduction1381
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Ethernet Frame1382
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MAC Operation1382
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Interrupts1385
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DMA Operation1386
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Register Map1387
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Features1410
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Introduction1410
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SSI Block Diagram1410
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SSI Block Diagram1411
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Bit Rate Generation1412
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FIFO Operation1412
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Interrupts1412
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Frame Formats1413
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DMA Operation1417
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SSI Base Addresses1419
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SSI Registers1419
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SSI_REGS Registers1420
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SSICR0 Register1422
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SSICR1 Register1424
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SSIDR Register1426
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SSISR Register1427
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SSICPSR Register1428
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SSIIM Register1429
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SSIRIS Register1430
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SSIMIS Register1432
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SSIICR Register1434
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SSIDMACTL Register1435
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SSIPV Register1436
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SSIPP Register1437
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SSIPC Register1438
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Ssipcellid0 Register1447
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Ssipcellid1 Register1448
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Ssipcellid2 Register1449
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Ssipcellid3 Register1450
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Block Diagram1452
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Introduction1452
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Baud-Rate Generation1454
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Data Transmission1454
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UART Character Frame1454
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Irda Data Modulation1455
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Serial IR (SIR)1455
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ISO 7816 Support1456
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LIN Message1456
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LIN Support1456
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FIFO Operation1457
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Interrupts1457
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DMA Operation1458
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Loopback Operation1458
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Register Map1460
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Register Map1461
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I2C Block Diagram1485
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Introduction1485
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Interrupts1489
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Loopback Operation1490
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Register Map1498
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Features1513
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Overview1513
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Block Diagram1514
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CAN Block Diagram1514
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Initialization1515
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Operating Modes1515
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Test Modes1516
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Can_Muxing1517
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Error Interrupts1521
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Debug Mode1522
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Message Handling1525
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CAN Bit Timing1529
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Bit Timing1530
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IF3 Register Set1539
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Message RAM1539
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Descriptions1549
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Cortex-M3 Processor1567
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Block Diagram1568
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Overview1568
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Overview1569
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Programming Model1570
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Register Map1570
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Stacks1570
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Link Register1573
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Data Types1578
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Memory Model1578
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Bit-Banding1581
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Bit-Band Mapping1582
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Data Storage1582
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Data Storage1583
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Exception Model1584
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Exception States1584
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Exception Types1584
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Interrupts1586
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Exception Handlers1588
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Vector Table1588
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Exception Priorities1589
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Vector Table1589
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Fault Handling1592
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Fault Types1592
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Faults1592
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Lockup1593
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Power Management1593
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Entering Sleep Modes1594
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Overview1599
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SRD Use Example1604
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Register Map1606
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