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F28M35M22C
Texas Instruments F28M35M22C Manuals
Manuals and User Guides for Texas Instruments F28M35M22C. We have
1
Texas Instruments F28M35M22C manual available for free PDF download: Technical Reference Manual
Texas Instruments F28M35M22C Technical Reference Manual (1655 pages)
Brand:
Texas Instruments
| Category:
Microcontrollers
| Size: 11.4 MB
Table of Contents
Section 1
2
Table of Contents
2
Section 2
9
Preface
78
System Control and Interrupts
79
Signal Description
80
Signals for System Control and Clocks
80
Device Identification
81
System Control Functional Description
81
Device Configuration Registers
82
Device Level Reset Sources
82
Master Subsystem Device Configuration
82
Reset Control
82
Device Level Reset Sources
83
Device Bring-Up Time Line
84
Resets Connectivity
88
Handling of Resets at System Level
89
Master Subsystem Rests, Signals and Effects
89
Control Subsystem Resets, Signals and Effects
92
WIR Mode
92
EMU0/1 Pin Values for wir Mode
93
Entering wir Mode
93
Exiting wir Mode
94
Master and Control Subsystem wir Mode Flow
94
Exceptions and Interrupts Control
95
Master Subsystem Nested Vectored Interrupt Controller
95
Master Subsystem Exceptions
96
Master Subsystem Exceptions Handling
96
Master Subsystem Non-Maskable Interrupt (MNMI) Module
97
Master Subsystem NMI Sources and MNMIWD
98
Control Subsystem PIE
100
PIE Interrupts Multiplexing
101
CPU Level Interrupt Handling
103
Enabling Interrupt
104
Interrupt Vector Table Mapping
104
Control Subsystem C28X Processor after Reset Flow
105
Vector Table Mapping after Reset Operation
105
PIE Interrupt Sources and External Interrupts XINT1/XINT2/XINT3
106
Multiplexed Interrupt Request Flow
108
PIE Vector Table
110
PIE Vector Table Mapping
110
Control Subsystem Exceptions Handling
116
Control Subsystem NMI (CNMI) Module
116
Control Subsystem NMI Sources and CNMIWD
117
Access to EALLOW-Protected Registers
119
Safety Features
119
Write Protection on Registers
119
Missing Clock Detection Logic
120
Reference Clock Limits for Detecting a Missing Clock
121
Missing Clock Detection Logic
122
Control Subsystem PIE Vector Address Validity Check
123
PLLSLIP Detection
123
ECC and Parity Enabled Rams, Shared Rams Protection
124
Nmiwds
124
Watchdog Timers
124
Clock Control
125
ECC Enabled Flash Memory
125
Power Control
125
Clock Sources
126
Plls
126
Master Subsystem Clocking
127
Master Subsystem Clocks and Low Power Mode Configuration
128
Control Subsystem Clocking
130
Control Subsystem Clocks and Low Power Mode Configuration
131
Control Subsystem Peripherals Clocking
133
Clocking Control Semaphore Functionality
134
ACIB and Analog Peripherals Clocking
135
Configuring XCLKOUT
135
32-Bit CPU Timers 0/1/2
136
CPU-Timer Interrupts Signals and Output Signal
136
CPU-Timers
136
CPU-Timers 0, 1, 2 Configuration and Control Registers
137
Timerxtim Register (X = 0, 1, 2)
137
Timerxtim Register Field Descriptions
137
Timerxtimh Register (X = 0, 1, 2)
137
Timerxprd Register (X = 0, 1, 2)
138
Timerxprd Register Field Descriptions
138
Timerxprdh Register (X = 0, 1, 2)
138
Timerxprdh Register Field Descriptions
138
Timerxtcr Register (X = 0, 1, 2)
138
Timerxtcr Register Field Descriptions
138
Timerxtimh Register Field Descriptions
138
Timerxtpr Register (X = 0, 1, 2)
139
Timerxtpr Register Field Descriptions
139
Device Low Power Modes for Active Power Reduction
140
Low Power Modes
140
Timerxtprh Register (X = 0, 1, 2)
140
Timerxtprh Register Field Descriptions
140
M3 Subsystem Low-Power Modes
141
Low-Power Modes Configuration
143
Code Security Module (CSM)
144
Functional Description
144
Master Subsystem Secure RAM Zone Selection
144
Security Levels
145
CSM Impact on Other On-Chip Resources
147
Incorporating Code Security in User Applications
147
M3 Zone1 - Reserved Locations in Flash Memory
147
OTPSECLOCK - Reserved Locations in OTP Memory
147
C28X - Reserved Locations in Flash Memory
148
M3 Zone2 - Reserved Locations in Flash Memory
148
CSM Password Match Flow
150
Zone Security Status
152
ECSL Password Match Flow
153
Do's and Don'ts to Protect Security Logic
155
Functional Description
155
Zone ECSL Status
155
Μcrc Module
155
CRC Calculation for Data Stored in Secure Memory
156
CRC Calculation Procedure
156
CRC Polynomials
156
Inter Processor Communications (IPC)
156
IPC Flags and Interrupts
157
IPC MSG RAM Read/Write Accesses
157
Msgrams
157
Messaging with IPC Flags and Interrupts
158
MTOCIPC Communication
158
CTOMIPC Communication
159
Examples for Software IPC Procedure
160
IPC Message Registers
160
CTOMIPC Message Registers
161
Flash Pump Semaphore
161
MTOCIPC Message Registers
161
Clock Configuration Semaphore
162
Flash Pump Allocation for Different States of Flash Pump Semaphore
162
Mastership of Clock Configuration Registers for Different States of Clock Configuration Semaphore
163
Free Running Counter
164
System Control Registers
165
System Control, Configuration Register Map
165
System Control, Configuration Registers Address Map
165
Device Identification 0 (DID0) Register
173
Device Identification 0 (DID0) Register Field Descriptions
173
Device Identification 1 (DID1) Register
173
Device Identification 1 (DID1) Register Field Descriptions
173
Device Identification and Device Configuration
173
Device Configuration 1 (DC1) Register
174
Device Configuration 1 (DC1) Register Field Descriptions
174
Device Configuration 2 (DC2) Register
175
Device Configuration 2 (DC2) Register Field Descriptions
175
Device Configuration 4 (DC4) Register
177
Device Configuration 4 (DC4) Register Field Descriptions
177
Device Configuration 10 (DC10) Register
179
Device Configuration 10 (DC10) Register Field Descriptions
179
Device Configuration 6 (DC6) Register
179
Device Configuration 6 (DC6) Register Field Descriptions
179
Device Configuration 7 (DC7) Register
180
Device Configuration 7 (DC7) Register Field Descriptions
180
Master Subsystem Configuration (MCNF) Register
180
Master Subsystem Configuration (MCNF) Register Field Descriptions
180
Master Subsystem: ACIB Status (MCIBSTATUS) Register Field Descriptions
181
Master Subystem: ACIB Status (MCIBSTATUS) Register
181
Serial Port Loop Back Control (SERPLOOP) Register
181
Serial Port Loop Back Control (SERPLOOP) Register Field Descriptions
181
C28 Device Part ID (PARTID) Register
182
C28 Device Part ID (PARTID) Register Field Descriptions
182
C28 Revision ID (REVID) Register
182
C28 Revision ID (REVID) Register Field Descriptions
182
Control Subsystem Device Configuration (DEVICECNF) Register
183
Control Subsystem Device Configuration (DEVICECNF) Register Field Descriptions
183
Control Subsystem Peripheral Configuration 0 (CCNF0) Register
183
Control Subsystem Peripheral Configuration 0 (CCNF0) Register Field Descriptions
184
Control Subsystem Peripheral Configuration 1 (CCNF1) Register
184
Control Subsystem Peripheral Configuration 1 (CCNF1) Register Field Descriptions
184
Control Subsystem Peripheral Configuration 2 (CCNF2) Register
185
Control Subsystem Peripheral Configuration 2 (CCNF2) Register Field Descriptions
185
Control Subsystem Peripheral Configuration 3 (CCNF3) Register
186
Control Subsystem Peripheral Configuration 3 (CCNF3) Register Field Descriptions
186
Control Subsystem Peripheral Configuration 4 (CCNF4) Register
187
Control Subsystem Peripheral Configuration 4 (CCNF4) Register Field Descriptions
187
Master Subsystem Memory Configuration (MEMCNF) Register
187
Master Subsystem Memory Configuration (MEMCNF) Register Field Descriptions
187
Control Subsystem Reset Status (CRESSTS) Register
188
Control Subsystem Reset Status (CRESSTS) Register Field Descriptions
188
Reset Control and Status Registers
188
Subsystem Reset Configuration/Control (CRESCNF) Register
188
Subsystem Reset Configuration/Control (CRESCNF) Register Field Descriptions
188
Master Reset Cause (MRESC) Register
190
Master Reset Cause (MRESC) Register Field Descriptions
190
C28 Reset Cause Register (CRESC) Register
191
C28 Reset Cause Register (CRESC) Register Field Descriptions
191
Software Reset Control 0 (SRCR0) Register
192
Software Reset Control 0 (SRCR0) Register Field Descriptions
192
Software Reset Control 1 (SRCR1) Register
193
Software Reset Control 1 (SRCR1) Register Field Descriptions
193
Software Reset Control 2 (SRCR2) Register
194
Software Reset Control 2 (SRCR2) Register Field Descriptions
194
Software Reset Control 3 (SRCR3) Register
195
Software Reset Control 3 (SRCR3) Register Field Descriptions
196
C28 Wait-In-Reset (CWIR) Register
197
C28 Wait-In-Reset (CWIR) Register Field Descriptions
197
Master Subsystem Wait-In-Reset (MWIR) Register
197
Master Subsystem Wait-In-Reset (MWIR) Register Field Descriptions
197
WIRMODE Registers
197
Exception and Interrupts
198
M3NMI Configuration (MNMICFG) Register
198
M3NMI Configuration (MNMICFG) Register Field Descriptions
198
M3NMI Flag (MNMIFLG) Register
199
M3NMI Flag (MNMIFLG) Register Field Descriptions
199
M3NMI Flag Clear (MNMIFLGCLR) Register
200
M3NMI Flag Clear (MNMIFLGCLR) Register Field Descriptions
200
M3NMI Flag Force (MNMIFLGFRC) Register
201
M3NMI Flag Force (MNMIFLGFRC) Register Field Descriptions
201
M3NMI Watchdog Counter (MNMIWDCNT) Register
202
M3NMI Watchdog Counter (MNMIWDCNT) Register Field Descriptions
202
M3NMI Watchdog Period (MNMIWDPRD) Register
202
M3NMI Watchdog Period (MNMIWDPRD) Register Field Descriptions
202
C28 NMI Configuration (CNMICFG) Register
203
C28 NMI Configuration (CNMICFG) Register Field Descriptions
203
C28 NMI Flag (CNMIFLG) Register
203
C28 NMI Flag (CNMIFLG) Register Field Descriptions
204
C28 NMI Flag Clear (CNMIFLGCLR) Register
205
C28 NMI Flag Clear (CNMIFLGCLR) Register Field Descriptions
205
C28 NMI Flag Force (CNMIFLGFRC) Register
206
C28 NMI Flag Force (CNMIFLGFRC) Register Field Descriptions
206
C28 NMI Watchdog Counter (CNMIWDCNT) Register
206
C28 NMI Watchdog Counter (CNMIWDCNT) Register Field Descriptions
206
C28 NMI Watchdog Period (CNMIWDPRD) Register
207
C28 NMI Watchdog Period (CNMIWDPRD) Register Field Descriptions
207
PIE, Acknowledge (PIEACK) Register
207
PIE, Control (PIECTRL) Register
207
PIE, Control (PIECTRL) Register Field Descriptions
207
PIE, Acknowledge (PIEACK) Register Field Descriptions
208
PIE, Intx Group Enable Register (Pieierx) (X = 1 to 12)
208
PIE, Intx Group Enable Register (Pieierx) (X = 1 to 12) Field Descriptions
208
PIE, Intx Group Flag Register (Pieifrx) (X = 1 to 12)
209
PIE, Intx Group Flag Register (Pieifrx) (X = 1 to 12) Field Descriptions
209
CPU Interrupt Flag Register (IFR)
210
CPU Interrupt Flag Register Field Descriptions (IFR)
210
CPU Interrupt Enable Register (IER)
212
CPU Interrupt Enable Register (IER) Field Descriptions
212
Debug Interrupt Enable Register (DBGIER)
213
Debug Interrupt Enable Register (DBGIER) Field Descriptions
213
C28 External Interrupt 1 Configuration Register (XINT1CR)
215
C28 External Interrupt 1 Configuration Register (XINT1CR) Field Descriptions
215
C28 External Interrupt 2 Configuration Register (XINT2CR)
215
C28 External Interrupt 2 Configuration Register (XINT2CR) Field Descriptions
215
C28 External Interrupt 3 Configuration Register (XINT3CR)
215
C28 External Interrupt 1 Counter Register (XINT1CTR)
216
C28 External Interrupt 1 Counter Register (XINT1CTR) Field Descriptions
216
C28 External Interrupt 2 Counter Register (XINT2CTR)
216
C28 External Interrupt 2 Counter Register (XINT2CTR) Field Descriptions
216
C28 External Interrupt 3 Configuration Register (XINT3CR) Field Descriptions
216
C28 External Interrupt 3 Counter Register (XINT3CTR)
217
C28 External Interrupt 3 Counter Register (XINT3CTR) Field Descriptions
217
System PLL Configuration (SYSPLLCTL) Register
217
System PLL Configuration (SYSPLLCTL) Register Field Descriptions
217
Control Subsystem Clock Disable (CCLKOFF) Register
218
Control Subsystem Clock Disable (CCLKOFF) Register Field Descriptions
218
M3 Configuration Lock (MLOCK) Register
218
M3 Configuration Write Allow (MWRALLOW) Register
218
M3 Configuration Write Allow (MWRALLOW) Register Field Descriptions
218
Safety Control Registers
218
M3 Configuration Lock (MLOCK) Register Field Descriptions
219
Missing Clock Force (MCLKFRCCLR) Register
219
Missing Clock Status (MCLKSTS) Register
219
Missing Clock Status (MCLKSTS) Register Field Descriptions
219
Missing Clock Enable (MCLKEN) Register
220
Missing Clock Enable (MCLKEN) Register Field Descriptions
220
Missing Clock Force (MCLKFRCCLR) Register Field Descriptions
220
Missing Clock Reference Limit (MCLKLIMIT) Register
220
C28 USER_SWREG1 Register
221
C28 USER_SWREG1 Register Field Descriptions
221
C28_USER_SWREG2 Register
221
C28_USER_SWREG2 Register Field Descriptions
221
Missing Clock Reference Limit (MCLKLIMIT) Register Field Descriptions
221
Clocking Control Registers
222
System Clock Divider (SYSDIVSEL) Register
222
System PLL Multiplier (SYSPLLMULT) Register
222
System PLL Multiplier (SYSPLLMULT) Register Field Descriptions
222
Master Subsystem Clock Divider (M3SSDIVSEL) Register
223
System Clock Divider (SYSDIVSEL) Register Field Descriptions
223
System PLL Lock Status (SYSPLLSTS) Register
223
System PLL Lock Status (SYSPLLSTS) Register Field Descriptions
223
Master Subsystem Clock Divider (M3SSDIVSEL) Register Field Descriptions
224
USB PLL Configuration (UPLLCTL) Register
224
XPLL CLKOUT Control (XPLLCLKCFG) Register
224
XPLL CLKOUT Control (XPLLCLKCFG) Register Field Descriptions
224
USB PLL Configuration (UPLLCTL) Register Field Descriptions
225
USB PLL Multiplier (UPLLMULT) Register
225
USB PLL Multiplier (UPLLMULT) Register Field Descriptions
225
Bit Clock Source Selection for CAN0 (CAN0BCLKSEL) Register
226
Bit Clock Source Selection for CAN0 (CAN0BCLKSEL) Register Field Descriptions
226
USB PLL Lock Status (UPLLSTS) Register
226
USB PLL Lock Status (UPLLSTS) Register Field Descriptions
226
Bit Clock Source Selection for CAN1 (CAN1BCLKSEL) Register
227
Bit Clock Source Selection for CAN1 (CAN1BCLKSEL) Register Field Descriptions
227
Master GPIO High Performance Bus Control (GPIOHBCTL) Register
227
Run Mode Clock Configuration (RCC) Register
227
Run Mode Clock Configuration (RCC) Register Field Descriptions
227
Master GPIO High Performance Bus Control (GPIOHBCTL) Register Field Descriptions
228
Run Mode Clock Gating Control Register 0 (RCGC0)
228
Run Mode Clock Gating Control Register 0 (RCGC0) Field Descriptions
228
Deep Sleep Mode Clock Gating Control Register 0 (DCGC0)
229
Deep Sleep Mode Clock Gating Control Register 0 (DCGC0) Field Descriptions
229
Sleep Mode Clock Gating Control Register 0 (SCGC0)
229
Sleep Mode Clock Gating Control Register 0 (SCGC0) Field Descriptions
229
Run Mode Clock Gating Control Register 1 (RCGC1)
230
Run Mode Clock Gating Control Register 1 (RCGC1) Field Descriptions
230
Sleep Mode Clock Gating Control Register 1 (SCGC1)
231
Sleep Mode Clock Gating Control Register 1 (SCGC1) Field Descriptions
231
Deep Sleep Mode Clock Gating Control Register 1 (DCGC1)
233
Deep Sleep Mode Clock Gating Control Register 1 (DCGC1) Field Descriptions
233
Run Mode Clock Gating Control Register 2 (RCGC2)
234
Run Mode Clock Gating Control Register 2 (RCGC2) Field Descriptions
234
Sleep Mode Clock Gating Control Register 2 (SCGC2)
236
Sleep Mode Clock Gating Control Register 2 (SCGC2) Field Descriptions
236
Deep Sleep Mode Clock Gating Control Register 2 (DCGC2)
238
Deep Sleep Mode Clock Gating Control Register 2 (DCGC2) Field Descriptions
238
Run Mode Clock Gating Control Register 3 (RCGC3)
239
Run Mode Clock Gating Control Register 3 (RCGC3) Field Descriptions
239
Sleep Mode Clock Gating Control Register 3 (SCGC3)
239
Deep Sleep Mode Clock Gating Control Register 3 (DCGC3)
240
Deep Sleep Mode Clock Gating Control Register 3 (DCGC3) Field Descriptions
240
Sleep Mode Clock Gating Control Register 3 (SCGC3) Field Descriptions
240
Deep Sleep Clock Configuration (DSLPCLKCFG) Register
241
Deep Sleep Clock Configuration (DSLPCLKCFG) Register Field Descriptions
241
C28 CPU Timer 2 Clock Configuration (CLKCTL) Register
242
C28 CPU Timer 2 Clock Configuration (CLKCTL) Register Field Descriptions
242
Peripheral Clock Control Register 0 (PCLKCR0)
242
Peripheral Clock Control Register 0 (PCLKCR0) Register Field Descriptions
243
Peripheral Clock Control Register 1 (PCLKCR1)
243
Peripheral Clock Control Register 1 (PCLKCR1) Register Field Descriptions
243
Peripheral Clock Control Register 2 (PCLKCR2)
244
Peripheral Clock Control Register 2 (PCLKCR2) Register Field Descriptions
244
Peripheral Clock Control Register 3 (PCLKCR3)
245
Peripheral Clock Control Register 3 (PCLKCR3) Register Field Descriptions
245
High-Speed Clock Prescaler (CHISPCP) Register
246
High-Speed Clock Prescaler (CHISPCP) Register Field Descriptions
246
Low-Speed Clock Prescaler (CLOSPCP) Register
246
Low-Speed Clock Prescaler (CLOSPCP) Register Field Descriptions
246
C28 XCLKOUT Divider Register (CXCLK)
247
C28 XCLKOUT Divider Register (CXCLK) Field Descriptions
247
Master Subsystem Code Security Module (CSM) Registers
248
Z1_CSMKEY0 Register
248
Z1_CSMKEY0 Register Field Descriptions
248
Z1_CSMKEY1 Register
248
Z1_CSMKEY1 Register Field Descriptions
248
Z1_CSMKEY2 Register
248
Z1_CSMKEY2 Register Field Descriptions
248
Z1_CSMKEY3 Register
248
Z1_CSMKEY3 Register Field Descriptions
249
Z1_ECSLKEY0 Register
249
Z1_ECSLKEY0 Register Field Descriptions
249
Z1_ECSLKEY1 Register
249
Z1_ECSLKEY1 Register Field Descriptions
249
Z2_CSMKEY0 Register
249
Z2_CSMKEY0 Register Field Descriptions
249
Z2_CSMKEY1 Register
250
Z2_CSMKEY1 Register Field Descriptions
250
Z2_CSMKEY2 Register
250
Z2_CSMKEY2 Register Field Descriptions
250
Z2_CSMKEY3 Register
250
Z2_CSMKEY3 Register Field Descriptions
250
Z2_ECSLKEY0 Register
250
Z1_CSMCR Register
251
Z1_CSMCR Register Field Descriptions
251
Z2_ECSLKEY0 Register Field Descriptions
251
Z2_ECSLKEY1 Register
251
Z2_ECSLKEY1 Register Field Descriptions
251
Z2_CSMCR Register
252
Z2_CSMCR Register Field Descriptions
253
Z1_GRABSECTR Register
254
Z1_GRABSECTR Register Field Descriptions
254
Z1_GRABRAMR Register
256
Z1_GRABRAMR Register Field Descriptions
256
Z2_GRABSECTR Register
257
Z2_GRABSECTR Register Field Descriptions
257
Z2_GRABRAMR Register
258
Z2_GRABRAMR Register Field Descriptions
258
Z1_EXEONLYR Register
260
Z1_EXEONLYR Register Field Descriptions
260
Z2_EXEONLYR Register
261
Z2_EXEONLYR Register Field Descriptions
261
OTPSECLOCK Register
262
OTPSECLOCK Register Field Descriptions
262
Control Subsystem Code Security Module (CSM) Registers
264
CSMKEY0 Register Field Descriptions
264
CSMKEY1 Register
264
CSMKEY1 Register Field Descriptions
264
CSMKEY2 Register
264
CSMKEY2 Register Field Descriptions
264
CSMKEY3 Register
264
Z1_CSMKEY0 Register
264
CSMCR Register
265
CSMCR Register Field Descriptions
265
CSMKEY3 Register Field Descriptions
265
ECSLKEY0 Register
266
ECSLKEY0 Register Field Descriptions
266
ECSLKEY1 Register
266
ECSLKEY1 Register Field Descriptions
266
EXEONLYR Register
267
EXEONLYR Register Field Description
267
Μcrc Register Description
268
Μcrc Register Summary
268
Μcrcconfig Register
269
Μcrcconfig Register Field Descriptions
269
Μcrccontrol Register
269
Μcrccontrol Register Field Descriptions
269
Μcrcres Register
269
M3 to C28 IPC Set (MTOCIPCSET) Field Descriptions
270
M3 to C28 IPC Set (MTOCIPCSET) Register
270
Master Subsystem IPC Registers
270
Μcrcres Register Field Descriptions
270
M3 to C28 IPC Clear (MTOCIPCCLR) Register
272
M3 to C28 IPC Clear (MTOCIPCCLR) Register Field Descriptions
272
M3 to C28 Core Flag (MTOCIPCFLG) Register
274
M3 to C28 Core Flag (MTOCIPCFLG) Register Field Descriptions
274
M3 to C28 Core IPC Acknowledge (CTOMIPCACK) Register
276
M3 to C28 Core IPC Acknowledge (CTOMIPCACK) Register Field Descriptions
276
C28 to M3 Core IPC Status (CTOMIPCSTS) Register
278
C28 to M3 Core IPC Status (CTOMIPCSTS) Register Field Descriptions
278
M3 Flash Semaphore Field Descriptions
280
M3 Flash Semaphore Register
280
Control Subsystem IPC Registers
281
CTOMIPCSET Register
281
M3 Clock Semaphore Register
281
M3 Flash Semaphore Field Descriptions
281
CTOMIPCSET Register Field Descriptions
282
CTOMIPCCLR Register
284
CTOMIPCCLR Register Field Descriptions
284
CTOMIPCFLG Register
286
CTOMIPCFLG Register Field Descriptions
286
MTOCIPCACK Register
288
MTOCIPCACK Register Field Descriptions
288
MTOCIPCSTS Register
290
MTOCIPCSTS Register Field Descriptions
290
C28 Flash Semaphore Field Descriptions
291
C28 Flash Semaphore Register
291
C28 Clock Semaphore Field Descriptions
292
C28 Clock Semaphore Register
292
CTOMIPCCOM Register
293
CTOMIPCCOM Register Field Descriptions
293
Master and Control Subsystem IPC Registers
293
MIPCCOUNTERH Register
293
MIPCCOUNTERH Register Field Descriptions
293
MIPCCOUNTERL Register
293
MIPCCOUNTERL Register Field Descriptions
293
CTOMIPCADDR Register
294
CTOMIPCADDR Register Field Descriptions
294
CTOMIPCDATAR Register
294
CTOMIPCDATAR Register Field Descriptions
294
CTOMIPCDATAW Register
294
CTOMIPCDATAW Register Field Descriptions
294
MTOCIPCCOM Register
294
MTOCIPCCOM Register Field Descriptions
295
CTOMIPCBOOTSTS Register
296
MTOCIPCADDR Register
296
MTOCIPCADDR Register Field Descriptions
296
MTOCIPCDATAR Register
296
MTOCIPCDATAR Register Field Descriptions
296
MTOCIPCDATAW Register
296
MTOCIPCDATAW Register Field Descriptions
296
CTOMIPCBOOTSTS Register Field Descriptions
297
MTOCIPCBOOTMODE Register Field Descriptions
297
Mtocipcbootmoderegister
297
M3 General-Purpose Timers
298
Block Diagram
299
GPTM Block Diagram
299
GPTM Features
299
Available CCP Pins
300
Functional Description
300
General-Purpose Timer Capabilities
300
GPTM Reset Conditions
300
16-Bit Timer with Prescaler Configurations
301
Timer Modes
301
Timer Daisy Chain
302
Edge-Count Mode Example
303
16-Bit Input Edge-Time Mode Example
304
16-Bit PWM Mode Example
305
DMA Operation
305
Accessing Concatenated Register Values
306
Initialization and Configuration
306
One-Shot/Periodic Timer Mode
306
Input Edge Timing Mode
307
Input Edge-Count Mode
307
Real-Time Clock (RTC) Mode
307
16-Bit PWM Mode
308
Register Map
308
Timers Register Map
308
GPTM Configuration (GPTMCFG) Register
309
GPTM Configuration (GPTMCFG) Register Field Descriptions
309
GPTM Configuration (GPTMCFG) Register, Offset 0X000
309
GPTM Timer a Mode (GPTMTAMR) Register, Offset 0X004
309
Register Descriptions
309
GPTM Timer a Mode (GPTMTAMR) Register
310
GPTM Timer a Mode (GPTMTAMR) Register Field Descriptions
310
GPTM Timer B Mode (GPTMTBMR) Register
311
GPTM Timer B Mode (GPTMTBMR) Register Field Descriptions
311
GPTM Timer B Mode (GPTMTBMR) Register, Offset 0X008
311
GPTM Control (GPTMCTL) Register
312
GPTM Control (GPTMCTL) Register Field Descriptions
312
GPTM Control (GPTMCTL) Register, Offset 0X00C
312
GPTM Interrupt Mask (GPTMIMR) Register
313
GPTM Interrupt Mask (GPTMIMR) Register Field Descriptions
313
GPTM Interrupt Mask (GPTMIMR) Register, Offset 0X018
313
GPTM Raw Interrupt Status (GPTMRIS) Register
314
GPTM Raw Interrupt Status (GPTMRIS) Register Field Descriptions
314
GPTM Raw Interrupt Status (GPTMRIS) Register, Offset 0X01C
314
GPTM Masked Interrupt Status (GPTMMIS) Register
315
GPTM Masked Interrupt Status (GPTMMIS) Register, Offset 0X020
315
GPTM Interrupt Clear (GPTMICR) Register, Offset 0X024
316
GPTM Masked Interrupt Status (GPTMMIS) Register Field Descriptions
316
GPTM Interrupt Clear (GPTMICR) Register
317
GPTM Interrupt Clear (GPTMICR) Register Field Descriptions
317
GPTM Timer a Interval Load (GPTMTAILR) Register, Offset 0X028
317
GPTM Timer a Interval Load (GPTMTAILR) Register
318
GPTM Timer a Interval Load (GPTMTAILR) Register Field Descriptions
318
GPTM Timer a Interval Load (GPTMTBILR) Register
318
GPTM Timer a Interval Load (GPTMTBILR) Register Field Descriptions
318
GPTM Timer a Match (GPTMTAMATCHR) Register, Offset 0X030
318
GPTM Timer B Interval Load (GPTMTBILR) Register, Offset 0X02C
318
GPTM Timer a Match (GPTMTAMATCHR) Register
319
GPTM Timer a Match (GPTMTAMATCHR) Register Field Descriptions
319
GPTM Timer a Prescale (GPTMTAPR) Register
319
GPTM Timer a Prescale (GPTMTAPR) Register, Offset 0X038
319
GPTM Timer B Match (GPTMTBMATCHR) Register
319
GPTM Timer B Match (GPTMTBMATCHR) Register Field Descriptions
319
GPTM Timer B Match (GPTMTBMATCHR) Register, Offset 0X034
319
GPTM Timer a Prescale (GPTMTAPR) Register Field Descriptions
320
GPTM Timer a Prescale (GPTMTBPR) Register
320
GPTM Timer a Prescale (GPTMTBPR) Register Field Descriptions
320
GPTM Timer a Prescale Match (GPTMTAPMR) Register
320
GPTM Timer a Prescale Match (GPTMTAPMR) Register Field Descriptions
320
GPTM Timer a Prescale Match (GPTMTAPMR) Register, Offset 0X040
320
GPTM Timer B Prescale (GPTMTBPR) Register, Offset 0X03C
320
GPTM Timer B Prescale Match (GPTMTBPMR) Register, Offset 0X044
320
GPTM Timer a (GPTMTAR) Register
321
GPTM Timer a (GPTMTAR) Register Field Descriptions
321
GPTM Timer a (GPTMTAR) Register, Offset 0X048
321
GPTM Timer B (GPTMTBR) Register, Offset 0X04C
321
GPTM Timer B Prescale Match (GPTMTBPMR) Register
321
GPTM Timer B Prescale Match (GPTMTBPMR) Register Field Descriptions
321
GPTM Timer a Value (GPTMTAV) Register
322
GPTM Timer a Value (GPTMTAV) Register Field Descriptions
322
GPTM Timer a Value (GPTMTAV) Register, Offset 0X050
322
GPTM Timer B (GPTMTBR) Register
322
GPTM Timer B (GPTMTBR) Register Field Descriptions
322
GPTM Timer B Value (GPTMTBV) Register, Offset 0X054
322
GPTM Timer B Value (GPTMTBV) Register
323
GPTM Timer B Value (GPTMTBV) Register Field Descriptions
323
M3 Watchdog Timers
324
Block Diagram
325
Introduction
325
Watchdog Timer Module Block Diagram
325
Functional Description
326
Initialization and Configuration
326
Register Map
326
Watchdog Load (WDTLOAD) Register
327
Watchdog Load (WDTLOAD) Register Field Descriptions
327
Watchdog Timers Register Map
327
Register Descriptions
328
Watchdog Value (WDTVALUE) Register
328
Watchdog Value (WDTVALUE) Register Field Descriptions
328
Watchdog Value (WDTVALUE) Register, Offset 0X004
328
Watchdog Control (WDTCTL) Register
329
Watchdog Control (WDTCTL) Register Field Descriptions
329
Watchdog Control (WDTCTL) Register, Offset 0X008
329
Watchdog Interrupt Clear (WDTICR) Register
329
Watchdog Interrupt Clear (WDTICR) Register Field Descriptions
329
Watchdog Interrupt Clear (WDTICR) Register, Offset 0X00C
329
Watchdog Masked Interrupt Status (WDTMIS) Register
330
Watchdog Masked Interrupt Status (WDTMIS) Register Field Descriptions
330
Watchdog Masked Interrupt Status (WDTMIS) Register, Offset 0X014
330
Watchdog Raw Interrupt Status (WDTRIS) Register
330
Watchdog Raw Interrupt Status (WDTRIS) Register Field Descriptions
330
Watchdog Raw Interrupt Status (WDTRIS) Register, Offset 0X010
330
Watchdog Lock (WDTLOCK) Register
331
Watchdog Lock (WDTLOCK) Register Field Descriptions
331
Watchdog Lock (WDTLOCK) Register, Offset 0Xc00
331
Watchdog Test (WDTTEST) Register
331
Watchdog Test (WDTTEST) Register Field Descriptions
331
Watchdog Test (WDTTEST) Register, Offset 0X418
331
Watchdog Peripheral Identification 4 (Wdtperiphid4) Register
332
Watchdog Peripheral Identification 4 (Wdtperiphid4) Register Field Descriptions
332
Watchdog Peripheral Identification 4 (Wdtperiphid4) Register, Offset 0Xfd0
332
Watchdog Peripheral Identification 5 (Wdtperiphid5) Register
332
Watchdog Peripheral Identification 5 (Wdtperiphid5) Register Field Descriptions
332
Watchdog Peripheral Identification 5 (Wdtperiphid5) Register, Offset 0Xfd4
332
Watchdog Peripheral Identification 6 (Wdtperiphid6) Register
332
Watchdog Peripheral Identification 6 (Wdtperiphid6) Register Field Descriptions
332
Watchdog Peripheral Identification 6 (Wdtperiphid6) Register, Offset 0Xfd8
332
Watchdog Peripheral Identification 0 (Wdtperiphid0) Register
333
Watchdog Peripheral Identification 0 (Wdtperiphid0) Register Field Descriptions
333
Watchdog Peripheral Identification 0 (Wdtperiphid0) Register, Offset 0Xfe0
333
Watchdog Peripheral Identification 1 (Wdtperiphid1) Register
333
Watchdog Peripheral Identification 1 (Wdtperiphid1) Register Field Descriptions
333
Watchdog Peripheral Identification 1 (Wdtperiphid1) Register, Offset 0Xfe4
333
Watchdog Peripheral Identification 7 (Wdtperiphid7) Register
333
Watchdog Peripheral Identification 7 (Wdtperiphid7) Register Field Descriptions
333
Watchdog Peripheral Identification 7 (Wdtperiphid7) Register, Offset 0Xfdc
333
Watchdog Peripheral Identification 2 (Wdtperiphid2) Register
334
Watchdog Peripheral Identification 2 (Wdtperiphid2) Register Field Descriptions
334
Watchdog Peripheral Identification 2 (Wdtperiphid2) Register, Offset 0Xfe8
334
Watchdog Peripheral Identification 3 (Wdtperiphid3) Register
334
Watchdog Peripheral Identification 3 (Wdtperiphid3) Register Field Descriptions
334
Watchdog Peripheral Identification 3 (Wdtperiphid3) Register, Offset 0Xfec
334
Watchdog Primecell Identification 0 (Wdtpcellid0) Register
334
Watchdog Primecell Identification 0 (Wdtpcellid0) Register Field Descriptions
334
Watchdog Primecell Identification 0 (Wdtpcellid0) Register, Offset 0Xff0
334
Watchdog Primecell Identification 1 (Wdtpcellid1) Register
335
Watchdog Primecell Identification 1 (Wdtpcellid1) Register Field Descriptions
335
Watchdog Primecell Identification 1 (Wdtpcellid1) Register, Offset 0Xff4
335
Watchdog Primecell Identification 2 (Wdtpcellid2) Register
335
Watchdog Primecell Identification 2 (Wdtpcellid2) Register Field Descriptions
335
Watchdog Primecell Identification 2 (Wdtpcellid2) Register, Offset 0Xff8
335
Watchdog Primecell Identification 3 (Wdtpcellid3) Register
335
Watchdog Primecell Identification 3 (Wdtpcellid3) Register Field Descriptions
335
Watchdog Primecell Identification 3 (Wdtpcellid3) Register, Offset 0Xffc
335
General-Purpose Input/Output (GPIO)
336
General-Purpose Input/Output (GPIO)
337
Introduction
337
Signal Description
337
GPIO Pins and Alternate Functions
338
GPIO Pins and Alternate Mode Functions
340
Functional Description
341
Digital I/O Pads
342
GPIODATA Read Example
343
GPIODATA Write Example
343
GPIO Pad Configuration Examples
345
Initialization and Configuration
345
GPIO Interrupt Configuration Example
346
Register Map
346
GPIO Register Map
347
GPIO Data (GPIODATA) Register
348
GPIO Data (GPIODATA) Register Field Descriptions
348
Register Descriptions
348
GPIO Direction (GPIODIR) Register
349
GPIO Direction (GPIODIR) Register Field Descriptions
349
GPIO Interrupt Sense (GPIOIS) Register
349
GPIO Interrupt Sense (GPIOIS) Register Field Descriptions
349
GPIO Interrupt both Edges (GPIOIBE) Register
350
GPIO Interrupt both Edges (GPIOIBE) Register Field Descriptions
350
GPIO Interrupt Event (GPIOIEV) Register
350
GPIO Interrupt Event (GPIOIEV) Register Field Descriptions
350
GPIO Interrupt Mask (GPIOIM) Register
351
GPIO Interrupt Mask (GPIOIM) Register Field Descriptions
351
GPIO Raw Interrupt Status (GPIORIS) Register
351
GPIO Raw Interrupt Status (GPIORIS) Register Field Descriptions
351
GPIO Interrupt Clear (GPIOICR) Register
352
GPIO Interrupt Clear (GPIOICR) Register Field Descriptions
352
GPIO Masked Interrupt Status (GPIOMIS) Register
352
GPIO Masked Interrupt Status (GPIOMIS) Register Field Descriptions
352
GPIO Alternate Function Select (GPIOAFSEL) Register
353
GPIO Alternate Function Select (GPIOAFSEL) Register Field Descriptions
353
GPIO Open Drain Select (GPIOODR) Register
354
GPIO Open Drain Select (GPIOODR) Register Field Descriptions
354
GPIO Pull-Up Select (GPIOPUR) Register
354
GPIO Digital Enable (GPIODEN) Register
355
GPIO Digital Enable (GPIODEN) Register Field Descriptions
355
GPIO Pull-Up Select (GPIOPUR) Register Field Descriptions
355
GPIO Lock (GPIOLOCK) Register
356
GPIO Lock (GPIOLOCK) Register Field Descriptions
356
GPIO Analog Mode Select (GPIOAMSEL) Register
357
GPIO Analog Mode Select (GPIOAMSEL) Register Field Descriptions
357
GPIO Commit (GPIOCR) Register
357
GPIO Commit (GPIOCR) Register Field Descriptions
357
GPIO Port Control (GPIOPCTL) Register
358
GPIO Port Control (GPIOPCTL) Register Field Descriptions
358
GPIO Alternate Peripheral Select (GPIOAPSEL) Register
359
GPIO Alternate Peripheral Select (GPIOAPSEL) Register Field Descriptions
359
GPIO Core Select (GPIOCSEL) Register
360
GPIO Core Select (GPIOCSEL) Register Field Descriptions
360
GPIO Peripheral Identification 4 (Gpioperiphid4) Register
361
GPIO Peripheral Identification 4 (Gpioperiphid4) Register Field Descriptions
361
GPIO Peripheral Identification 5 (Gpioperiphid5) Register
362
GPIO Peripheral Identification 5 (Gpioperiphid5) Register Field Descriptions
362
GPIO Peripheral Identification 6 (Gpioperiphid6) Register
363
GPIO Peripheral Identification 6 (Gpioperiphid6) Register Field Descriptions
363
GPIO Peripheral Identification 7 (Gpioperiphid7) Register
364
GPIO Peripheral Identification 7 (Gpioperiphid7) Register Field Descriptions
364
GPIO Peripheral Identification 0 (Gpioperiphid0) Register
365
GPIO Peripheral Identification 0 (Gpioperiphid0) Register Field Descriptions
365
GPIO Peripheral Identification 1 (Gpioperiphid1) Register
365
GPIO Peripheral Identification 1 (Gpioperiphid1) Register Field Descriptions
365
GPIO Peripheral Identification 2 (Gpioperiphid2) Register
366
GPIO Peripheral Identification 2 (Gpioperiphid2) Register Field Descriptions
366
GPIO Peripheral Identification 3 (Gpioperiphid3) Register
366
GPIO Peripheral Identification 3 (Gpioperiphid3) Register Field Descriptions
366
GPIO Primecell Identification 0 (Gpiopcellid0) Register
367
GPIO Primecell Identification 0 (Gpiopcellid0) Register Register Field Descriptions
367
GPIO Primecell Identification 1 (Gpiopcellid1) Register
367
GPIO Primecell Identification 1 (Gpiopcellid1) Register Register Field Descriptions
367
GPIO Primecell Identification 2 (Gpiopcellid2) Register
367
GPIO Primecell Identification 2 (Gpiopcellid2) Register Register Field Descriptions
368
GPIO Primecell Identification 3 (Gpiopcellid3) Register
368
GPIO Primecell Identification 3 (Gpiopcellid3) Register Register Field Descriptions
368
C28 General-Purpose Input/Output (GPIO)
369
GPIO Module Overview
369
Introduction
369
GPIO0 to GPIO31 Multiplexing Diagram
370
GPIO32, GPIO33 Multiplexing Diagram
371
GPIO34, GPIO135 Multiplexing Diagram
372
Analog/Gpio Multiplexing
373
GPIO MUX-To-Trip Input Connectivity
374
Configuration Overview
375
GPIO Control Registers
375
GPIO Trip Input Select Registers
375
Digital General Purpose I/O Control
378
GPIO Data Registers
378
Input Qualification
380
Input Qualification Using a Sampling Window
380
Sampling Frequency
381
Sampling Period
381
Case 1: Three-Sample Sampling Window Width
382
Case 2: Six-Sample Sampling Window Width
382
Input Qualifier Clock Cycles
383
Default State of Peripheral Input
385
Gpioa Mux
386
Gpiob Mux
387
Gpioc Mux
388
Analog MUX
389
Gpioe Mux
389
GPIO Port a Multiplexing 1 (GPAMUX1) Register Field Descriptions
391
GPIO Port a MUX 1 (GPAMUX1) Register
391
GPIO Port a MUX 2 (GPAMUX2) Register
393
GPIO Port a MUX 2 (GPAMUX2) Register Field Descriptions
393
GPIO Port B MUX 1 (GPBMUX1) Register
395
GPIO Port B MUX 1 (GPBMUX1) Register Field Descriptions
395
GPIO Port B MUX 2 (GPBMUX2) Register
397
GPIO Port B MUX 2 (GPBMUX2) Register Field Descriptions
397
GPIO Port C MUX 1 (GPCMUX1) Register
399
GPIO Port C MUX 1 (GPCMUX1) Register Field Descriptions
399
GPIO Port E MUX 1 (GPEMUX1) Register
400
GPIO Port E MUX 1 (GPEMUX1) Register Field Descriptions
400
Analog I/O MUX 1 (AIOMUX1) Register
401
Analog I/O MUX 1 (AIOMUX1) Register Field Descriptions
401
Analog I/O MUX 2 (AIOMUX2) Register
402
Analog I/O MUX 2 (AIOMUX2) Register Field Descriptions
402
GPIO Port a Qualification Control (GPACTRL) Register
403
GPIO Port a Qualification Control (GPACTRL) Register Field Descriptions
403
GPIO Port B Qualification Control (GPBCTRL) Register
404
GPIO Port B Qualification Control (GPBCTRL) Register Field Descriptions
404
GPIO Port C Qualification Control (GPCCTRL) Register
405
GPIO Port C Qualification Control (GPCCTRL) Register Field Descriptions
405
GPIO Port E Qualification Control (GPECTRL) Register
405
GPIO Port E Qualification Control (GPECTRL) Register Field Descriptions
405
GPIO Port a Qualification Select 1 (GPAQSEL1) Register
406
GPIO Port a Qualification Select 1 (GPAQSEL1) Register Field Descriptions
406
GPIO Port a Qualification Select 2 (GPAQSEL2) Register
406
GPIO Port a Qualification Select 2 (GPAQSEL2) Register Field Descriptions
406
GPIO Port B Qualification Select 1 (GPBQSEL1) Register
407
GPIO Port B Qualification Select 1 (GPBQSEL1) Register Field Descriptions
407
GPIO Port B Qualification Select 2 (GPBQSEL2) Register
407
GPIO Port B Qualification Select 2 (GPBQSEL2) Register Field Descriptions
407
GPIO Port C Qualification Select 1 (GPCQSEL1) Register
408
GPIO Port C Qualification Select 1 (GPCQSEL1) Register Field Descriptions
408
GPIO Port a Direction (GPADIR) Register
409
GPIO Port E Qualification Select 1 (GPEQSEL1) Register
409
GPIO Port E Qualification Select 1 (GPEQSEL1) Register Field Descriptions
409
GPIO Port a Direction (GPADIR) Register Field Descriptions
410
GPIO Port B Direction (GPBDIR) Register
410
GPIO Port B Direction (GPBDIR) Register Field Descriptions
410
GPIO Port C Direction (GPCDIR) Register
410
GPIO Port C Direction (GPCDIR) Register Field Descriptions
411
GPIO Port E Direction (GPEDIR) Register
411
GPIO Port E Direction (GPEDIR) Register Field Descriptions
411
SPRUH22I - April 2012 - Revised November 2019
411
Analog I/O dir (AIODIR) Register
412
Analog I/O dir (AIODIR) Register Field Descriptions
412
GPIO Port E Pullup Disable (GPEPUD)
412
GPIO Port E Pullup Disable (GPEPUD) Register Field Descriptions
412
GPIO Port a Data (GPADAT) Register
413
GPIO Port a Data (GPADAT) Register Field Descriptions
413
GPIO Port B Data (GPBDAT) Register
414
GPIO Port B Data (GPBDAT) Register Field Descriptions
414
GPIO Port C Data (GPCDAT) Register
415
GPIO Port C Data (GPCDAT) Register Field Descriptions
415
GPIO Port E Data (GPEDAT) Register
416
GPIO Port E Data (GPEDAT) Register Field Descriptions
416
Analog I/O DAT (AIODAT) Register
417
Analog I/O DAT (AIODAT) Register Field Descriptions
417
GPIO Port a Clear (GPACLEAR) Register Field Descriptions
418
GPIO Port a Set (GPASET) Register Field Descriptions
418
GPIO Port a Set, Clear and Toggle (GPASET, GPACLEAR, GPATOGGLE) Registers
418
GPIO Port a Toggle (GPATOGGLE) Register Field Descriptions
418
GPIO Port B Clear (GPBCLEAR) Register Field Descriptions
419
GPIO Port B Set (GPBSET) Register Field Descriptions
419
GPIO Port B Set, Clear and Toggle (GPBSET, GPBCLEAR, GPBTOGGLE) Registers
419
GPIO Port B Toggle (GPBTOGGLE) Register Field Descriptions
419
GPIO Port C Clear (GPCCLEAR) Register Field Descriptions
420
GPIO Port C Set (GPCSET) Register Field Descriptions
420
GPIO Port C Set, Clear and Toggle (GPCSET, GPCCLEAR, GPCTOGGLE) Registers
420
GPIO Port C Toggle (GPCTOGGLE) Register Field Descriptions
420
GPIO Port E Clear (GPECLEAR) Register Field Descriptions
421
GPIO Port E Set (GPESET) Register Field Descriptions
421
GPIO Port E Set, Clear and Toggle (GPESET, GPECLEAR, GPETOGGLE) Registers
421
GPIO Port E Toggle (GPETOGGLE) Register Field Descriptions
421
Analog I/O Clear (AIOCLEAR) Register Field Descriptions
422
Analog I/O Set (AIOSET) Register Field Descriptions
422
Analog I/O Toggle (AIOSET, AIOCLEAR, AIOTOGGLE) Register
422
Analog I/O Toggle (AIOTOGGLE) Register Field Descriptions
422
GPIO Trip Input Select Register (Gptripxsel)
423
GPIO Trip Input Select Register (Gptripxsel) Field Descriptions
423
GPTRIP Input Signals
423
GPIO Low Power Mode Wakeup Select 1 (GPIOLPMSEL1) Register
424
GPIO Low Power Mode Wakeup Select 1 (GPIOLPMSEL1) Register Field Descriptions
424
GPIO Low Power Mode Wakeup Select 2 (GPIOLPMSEL2) Register
424
GPIO Low Power Mode Wakeup Select 2 (GPIOLPMSEL2) Register Field Descriptions
424
RAM Control
426
Master Access for Sx RAM (Assuming All Other Protections Are Disabled)
427
Shared RAM (Dedicated to Subsystem)
427
Shared RAM (Shared between Subsystems)
427
Error Handling in Different Scenarios
432
Mapping of ECC Bits in Read Data from Ecc/Parity Address Map
433
Mapping of Parity Bits in Read Data from Ecc/Parity Address Map
433
M3 RAM Configuration Registers Summary
434
M3 RAM Error Registers Summary
434
C28X RAM Configuration Registers Summary
435
C28X RAM Error Registers Summary
435
CX DEDRAM Configuration Register 1 (Cxdrcr1)
437
CX DEDRAM Configuration Register 1 (Cxdrcr1) Field Descriptions
437
CX SHRAM Configuration Register 1 (Cxsrcr1)
438
CX SHRAM Configuration Register 1 (Cxsrcr1) Field Descriptions
438
Sx SHRAM Master Select Register (Msxmsel)
439
Sx SHRAM Master Select Register (Msxmsel) Field Descriptions
439
M3 Sx SHRAM Configuration Register 1 (Msxsrcr1)
440
M3 Sx SHRAM Configuration Register 1 (Msxsrcr1) Field Descriptions
440
M3 Sx SHRAM Configuration Register 2 (Msxsrcr2)
442
M3 Sx SHRAM Configuration Register 2 (Msxsrcr2) Field Descriptions
442
M3TOC28_MSG_RAM Configuration Register (MTOCMSGRCR)
444
M3TOC28_MSG_RAM Configuration Register (MTOCMSGRCR) Field Descriptions
444
CX RAM Test and Initialization Register 1 (Cxrtestinit1)
445
CX RAM Test and Initialization Register 1 (Cxrtestinit1) Field Descriptions
445
M3 Sx RAM Test and Initialization Register 1 (Msxrtestinit1)
446
M3 Sx RAM Test and Initialization Register 1 (Msxrtestinit1) Field Descriptions
446
MTOC_MSG_RAM Test and Initialization Register (MTOCRTESTINIT)
448
MTOC_MSG_RAM Test and Initialization Register (MTOCRTESTINIT) Field Descriptions
448
CX RAM INITDONE Register 1 (Cxrinitdone1)
449
CX RAM INITDONE Register 1 (Cxrinitdone1) Field Descriptions
449
M3 Sx RAM INITDONE Register 1 (Msxrinitdone1)
450
M3 Sx RAM INITDONE Register 1 (Msxrinitdone1) Field Descriptions
450
M3 CPU Uncorrectable Write Error Address Register (MCUNCWEADDR)
452
M3 CPU Uncorrectable Write Error Address Register (MCUNCWEADDR) Field Descriptions
452
M3 Μdma Uncorrectable Write Error Address Register (MDUNCWEADDR)
452
M3 Μdma Uncorrectable Write Error Address Register (MDUNCWEADDR) Field Descriptions
452
MTOC_MSG_RAM INITDONE Register (MTOCRINITDONE)
452
MTOC_MSG_RAM INITDONE Register (MTOCRINITDONE) Field Descriptions
452
M3 CPU Uncorrectable Read Error Address Register (MCUNCREADDR)
453
M3 CPU Uncorrectable Read Error Address Register (MCUNCREADDR) Field Descriptions
453
M3 Μdma Uncorrectable Read Error Address Register (MDUNCREADDR)
453
M3 Μdma Uncorrectable Read Error Address Register (MDUNCREADDR) Field Descriptions
453
M3 CPU Corrected Read Error Address Register (MCPUCREADDR)
454
M3 CPU Corrected Read Error Address Register (MCPUCREADDR) Field Descriptions
454
M3 Μdma Corrected Read Error Address Register (MDMACREADDR)
454
M3 Μdma Corrected Read Error Address Register (MDMACREADDR) Field Descriptions
454
M3 Uncorrectable Error Flag Register (MUEFLG)
455
M3 Uncorrectable Error Flag Register (MUEFLG) Field Descriptions
455
M3 Uncorrectable Error Force Register (MUEFRC)
456
M3 Uncorrectable Error Force Register (MUEFRC) Field Descriptions
456
M3 Corrected Error Counter Register (MCECNTR)
457
M3 Corrected Error Counter Register (MCECNTR) Field Descriptions
457
M3 Uncorrectable Error Flag Clear Register (MUECLR)
457
M3 Uncorrectable Error Flag Clear Register (MUECLR) Field Descriptions
457
M3 Corrected Error Threshold Exceeded Flag Register (MCEFLG)
458
M3 Corrected Error Threshold Exceeded Flag Register (MCEFLG) Field Descriptions
458
M3 Corrected Error Threshold Exceeded Force Register (MCEFRC)
458
M3 Corrected Error Threshold Exceeded Force Register (MCEFRC) Field Descriptions
458
M3 Corrected Error Threshold Register (MCETRES)
458
M3 Corrected Error Threshold Register (MCETRES) Field Descriptions
458
M3 Corrected Error Threshold Exceeded Flag Clear Register (MCECLR)
459
M3 Corrected Error Threshold Exceeded Flag Clear Register (MCECLR) Field Descriptions
459
M3 Single Error Interrupt Enable Register (MCEIE)
459
M3 Single Error Interrupt Enable Register (MCEIE) Field Descriptions
459
Non-Master Access Violation Flag Clear Register (MNMAVCLR)
460
Non-Master Access Violation Flag Clear Register (MNMAVCLR) Field Descriptions
460
Non-Master Access Violation Flag Register (MNMAVFLG)
460
Non-Master Access Violation Flag Register (MNMAVFLG) Field Descriptions
460
Master Access Violation Flag Register (MMAVFLG)
461
Master Access Violation Flag Register (MMAVFLG) Field Descriptions
461
Master Access Violation Flag Clear Register (MMAVCLR)
462
Master Access Violation Flag Clear Register (MMAVCLR) Field Descriptions
462
Non-Master CPU Write Access Violation Address Register (MNMWRAVADDR)
462
Non-Master CPU Write Access Violation Address Register (MNMWRAVADDR) Field Descriptions
462
Master CPU Write Access Violation Address Register (MMWRAVADDR)
463
Master CPU Write Access Violation Address Register (MMWRAVADDR) Field Descriptions
463
Non-Master CPU Fetch Access Violation Address Register (MNMFAVADDR)
463
Non-Master CPU Fetch Access Violation Address Register (MNMFAVADDR) Field Descriptions
463
Non-Master DMA Write Access Violation Address Register (MNMDMAWRAVADDR)
463
Non-Master DMA Write Access Violation Address Register (MNMDMAWRAVADDR) Field Descriptions
463
Master CPU Fetch Access Violation Address Register (MMFAVADDR)
464
Master CPU Fetch Access Violation Address Register (MMFAVADDR) Field Descriptions
464
Master DMA Write Access Violation Address Register (CMDMAWRAVADDR) Field Descriptions
464
Master DMA Write Access Violation Address Register (MMDMAWRAVADDR)
464
Lx DEDRAM Configuration Register 1 (Lxdrcr1)
465
Lx DEDRAM Configuration Register 1 (Lxdrcr1) Field Descriptions
465
Lx SHRAM Configuration Register 1 (Lxsrcr1)
466
Lx SHRAM Configuration Register 1 (Lxsrcr1) Field Descriptions
466
C28X Sx SHRAM Master Select Register (Csxmsel)
467
C28X Sx SHRAM Master Select Register (Csxmsel) Field Descriptions
467
C28X Sx SHRAM Configuration Register 1 (Csxsrcr1)
468
C28X Sx SHRAM Configuration Register 1 (Csxsrcr1) Field Descriptions
468
C28X Sx SHRAM Configuration Register 2 (Csxsrcr2)
469
C28X Sx SHRAM Configuration Register 2 (Csxsrcr2) Field Descriptions
470
C28TOC28_MSG_RAM Configuration Register (CTOMMSGRCR)
471
C28TOC28_MSG_RAM Configuration Register (CTOMMSGRCR) Field Descriptions
471
M0, M1 and C28T0C28_MSG_RAM Test and Initialization Register (C28RTESTINIT)
472
M0, M1 and C28T0C28_MSG_RAM Test and Initialization Register (C28RTESTINIT) Field Descriptions
472
Lx RAM Test and Initialization Register 1 (Clxrtestinit1)
473
Lx RAM Test and Initialization Register 1 (Clxrtestinit1) Field Descriptions
473
C28X Sx RAM Test and Initialization Register 1 (Csxrtestinit1)
474
C28X Sx RAM Test and Initialization Register 1 (Csxrtestinit1) Field Descriptions
474
M0, M1 and C28T0M3_MSG_RAM INIT Done Register (C28RINITDONE)
476
M0, M1 and C28T0M3_MSG_RAM INIT Done Register (C28RINITDONE) Field Descriptions
476
C28X Lx RAM_INIT_DONE Register 1 (Clxrinitdone1)
477
C28X Lx RAM_INIT_DONE Register 1 (Clxrinitdone1) Field Descriptions
477
C28X Sx RAM_INIT_DONE Register 1 (Csxrinitdone1)
478
C28X Sx RAM_INIT_DONE Register 1 (Csxrinitdone1) Field Descriptions
478
C28X CPU Corrected Read Error Address Register (CCPUCREADDR)
480
C28X CPU Corrected Read Error Address Register (CCPUCREADDR) Field Descriptions
480
C28X CPU Uncorrectable Read Error Address Register (CCUNCREADDR)
480
C28X CPU Uncorrectable Read Error Address Register (CCUNCREADDR) Field Descriptions
480
C28X DMA Uncorrectable Read Error Address Register (CDUNCREADDR)
480
C28X DMA Uncorrectable Read Error Address Register (CDUNCREADDR) Field Descriptions
480
C28X DMA Corrected Read Error Address Register (CDMACREADDR)
481
C28X DMA Corrected Read Error Address Register (CDMACREADDR) Field Descriptions
481
C28X Uncorrectable Error Flag Register (CUEFLG)
481
C28X Uncorrectable Error Flag Register (CUEFLG) Field Descriptions
481
C28X Uncorrectable Error Flag Clear Register (CUECLR)
482
C28X Uncorrectable Error Flag Clear Register (CUECLR) Field Descriptions
482
C28X Uncorrectable Error Force Register (CUEFRC)
482
C28X Uncorrectable Error Force Register (CUEFRC) Field Descriptions
482
C28X Corrected Error Counter Register (CCECNTR)
483
C28X Corrected Error Counter Register (CCECNTR) Field Descriptions
483
C28X Corrected Error Threshold Register (CCETRES)
483
C28X Corrected Error Threshold Register (CCETRES) Field Descriptions
483
C28X Corrected Error Threshold Exceeded Flag Register (CCEFLG)
484
C28X Corrected Error Threshold Exceeded Flag Register (CCEFLG) Field Descriptions
484
C28X Corrected Error Threshold Exceeded Force Register (CCEFRC)
484
C28X Corrected Error Threshold Exceeded Force Register (CCEFRC) Field Descriptions
484
C28X Corrected Error Threshold Exceeded Flag Clear Register (CCECLR)
485
C28X Corrected Error Threshold Exceeded Flag Clear Register (CCECLR) Field Descriptions
485
C28X Single Error Interrupt Enable Register (CCEIE)
485
C28X Single Error Interrupt Enable Register (CCEIE) Field Descriptions
485
Non-Master Access Violation Flag Register (CNMAVFLG)
486
Non-Master Access Violation Flag Register (CNMAVFLG) Field Descriptions
486
Non-Master Access Violation Flag Clear Register (CNMAVCLR)
487
Non-Master Access Violation Flag Clear Register (CNMAVCLR) Field Descriptions
487
Non-Master Access Violation Force Register (CNMAVFRC)
487
Non-Master Access Violation Force Register (CNMAVFRC) Field Descriptions
487
Master Access Violation Flag Register (CMAVFLG)
488
Master Access Violation Flag Register (CMAVFLG) Field Descriptions
488
Master Access Violation Force Register (CMAVFRC)
488
Master Access Violation Force Register (CMAVFRC) Field Descriptions
488
Master Access Violation Flag Clear Register (CMAVCLR)
490
Master Access Violation Flag Clear Register (CMAVCLR) Field Descriptions
490
Non-Master CPU Fetch Access Violation Address Register (CNMFAVADDR)
491
Non-Master CPU Fetch Access Violation Address Register (CNMFAVADDR) Field Descriptions
491
Non-Master CPU Write Access Violation Address Register (CNMWRAVADDR)
491
Non-Master CPU Write Access Violation Address Register (CNMWRAVADDR) Field Descriptions
491
Non-Master DMA Write Access Violation Address Register (CNMDMAWRAVADDR)
491
Non-Master DMA Write Access Violation Address Register (CNMDMAWRAVADDR) Field Descriptions
491
Master CPU Fetch Access Violation Address Register (CMFAVADDR)
492
Master CPU Fetch Access Violation Address Register (CMFAVADDR) Field Descriptions
492
Master CPU Write Access Violation Address Register (CMWRAVADDR)
492
Master CPU Write Access Violation Address Register (CMWRAVADDR) Field Descriptions
492
Master DMA Write Access Violation Address Register (CMDMAWRAVADDR)
492
Master DMA Write Access Violation Address Register (CMDMAWRAVADDR) Field Descriptions
492
Programmable OTP Locations in M3 OTP
494
FMC Interface with Core, Bank and Pump
495
Flash Cache Mode
498
Flash Prefetch Mode
501
ECC Logic Inputs and Outputs
504
Flash Registers Memory Map on Master Subsystem
508
Flash Registers Memory Map on Control Subsystem
509
Flash Read Control Register (FRDCNTL)
512
Flash Read Control Register (FRDCNTL) Field Descriptions
512
Flash Read Margin Control Register (FSPRD)
512
Flash Read Margin Control Register (FSPRD) Field Descriptions
512
Flash Bank Access Control Register (FBAC)
513
Flash Bank Access Control Register (FBAC) Field Descriptions
513
Flash Bank Fallback Power Register (FBFALLBACK)
513
Flash Bank Fallback Power Register (FBFALLBACK) Field Description
513
Flash Bank Pump Control Register (FBPRDY)
514
Flash Bank Pump Control Register (FBPRDY) Field Descriptions
514
Flash Bank Pump Control Register 1 (FPAC1)
514
Flash Bank Pump Control Register 1 (FPAC1) Field Descriptions
514
Flash Bank Pump Control Register 2 (FPAC2)
515
Flash Bank Pump Control Register 2 (FPAC2) Field Descriptions
515
Flash Module Access Control Register (FMAC)
515
Flash Module Access Control Register (FMAC) Field Descriptions
515
SECZONEREQUEST(SEM) Register
516
SECZONEREQUEST(SEM) Register Field Descriptions
516
Flash Read Interface Control Register (FRD_INTF_CTRL)
517
Flash Read Interface Control Register (FRD_INTF_CTRL) Field Descriptions
517
ECC Enable Register (Ecc_Enable)
518
ECC Enable Register (Ecc_Enable) Field Descriptions
518
Single Error Address Register (SINGLE_ERR_ADDR)
518
Single Error Address Register (SINGLE_ERR_ADDR) Field Descriptions
518
Uncorrectable Error Address Register (UNC_ERR_ADDR)
518
Uncorrectable Error Address Register (UNC_ERR_ADDR) Field Descriptions
518
Error Position Register (ERR_POS)
519
Error Position Register (ERR_POS) Field Descriptions
519
Error Status Register (ERR_STATUS)
519
Error Status Register (ERR_STATUS) Field Descriptions
519
Error Counter Register (ERR_CNT)
520
Error Counter Register (ERR_CNT) Field Descriptions
520
Error Status Clear Register (ERR_STATUS_CLR)
520
Error Status Clear Register (ERR_STATUS_CLR) Field Descriptions
520
Error Interrupt Flag Register (ERR_INTFLG)
521
Error Interrupt Flag Register (ERR_INTFLG) Field Descriptions
521
Error Threshold Register (ERR_THRESHOLD)
521
Error Threshold Register (ERR_THRESHOLD) Field Descriptions
521
Data High Test Register (FDATAH_TEST)
522
Data High Test Register (FDATAH_TEST) Field Descriptions
522
Data Low Test Register (FDATAL_TEST)
522
Data Low Test Register (FDATAL_TEST) Field Descriptions
522
Error Interrupt Flag Clear Register (ERR_INTCLR)
522
Error Interrupt Flag Clear Register (ERR_INTCLR) Field Descriptions
522
ECC Control Register (FECC_CTRL)
523
ECC Control Register (FECC_CTRL) Field Descriptions
523
ECC Test Address Register (FADDR_TEST)
523
ECC Test Address Register (FADDR_TEST) Field Descriptions
523
ECC Test Register (FECC_TEST)
523
ECC Test Register (FECC_TEST) Field Descriptions
523
ECC Status Register (FECC_STATUS)
524
ECC Status Register (FECC_STATUS) Field Descriptions
524
Test Data out High Register (FECC_FOUTH_TEST)
524
Test Data out High Register (FECC_FOUTH_TEST) Field Descriptions
524
Test Data out Low Register (FECC_FOUTL_TEST)
524
Test Data out Low Register (FECC_FOUTL_TEST) Field Descriptions
524
Flash Read Control Register (FRDCNTL)
525
Flash Read Control Register (FRDCNTL) Field Descriptions
525
Flash Read Margin Control Register (FSPRD)
525
Flash Read Margin Control Register (FSPRD) Field Descriptions
525
Flash Bank Access Control Register (FBAC)
526
Flash Bank Access Control Register (FBAC) Field Descriptions
526
Flash Bank Fallback Power Register (FBFALLBACK)
526
Flash Bank Fallback Power Register (FBFALLBACK) Field Descriptions
526
Flash Bank Pump Control Register (FBPRDY)
527
Flash Bank Pump Control Register (FBPRDY) Field Descriptions
527
Flash Bank Pump Control Register 1 (FPAC1)
527
Flash Bank Pump Control Register 1 (FPAC1) Field Descriptions
527
Flash Bank Pump Control Register 2 (FPAC2)
528
Flash Bank Pump Control Register 2 (FPAC2) Field Descriptions
528
Flash Module Access Control Register (FMAC)
528
Flash Module Access Control Register (FMAC) Field Descriptions
528
Flash Read Interface Control Register (FRD_INTF_CTRL)
528
ECC Enable Register (ECC_ENABLE)
529
ECC Enable Register (ECC_ENABLE) Field Descriptions
529
Flash Read Interface Control Register (FRD_INTF_CTRL) Field Descriptions
529
Single Error Address Register (SINGLE_ERR_ADDR)
529
Single Error Address Register (SINGLE_ERR_ADDR) Field Descriptions
529
Uncorrectable Error Address Register (UNC_ERR_ADDR)
529
Uncorrectable Error Address Register (UNC_ERR_ADDR) Field Descriptions
529
Error Position Register (ERR_POS)
530
Error Position Register (ERR_POS) Field Descriptions
530
Error Status Register (ERR_STATUS)
530
Error Status Register (ERR_STATUS) Field Descriptions
530
Error Counter Register (ERR_CNT)
531
Error Counter Register (ERR_CNT) Field Descriptions
531
Error Status Clear Register (ERR_STATUS_CLR)
531
Error Status Clear Register (ERR_STATUS_CLR) Field Descriptions
531
Error Threshold Register (ERR_THRESHOLD)
531
Error Interrupt Flag Clear Register (ERR_INTCLR)
532
Error Interrupt Flag Clear Register (ERR_INTCLR) Field Descriptions
532
Error Interrupt Flag Register (ERR_INTFLG)
532
Error Interrupt Flag Register (ERR_INTFLG) Field Descriptions
532
Error Threshold Register (ERR_THRESHOLD) Field Descriptions
532
Data High Test Register (FDATAH_TEST)
533
Data High Test Register (FDATAH_TEST) Field Descriptions
533
Data Low Test Register (FDATAL_TEST)
533
Data Low Test Register (FDATAL_TEST) Field Descriptions
533
ECC Test Address Register (FADDR_TEST)
533
ECC Test Address Register (FADDR_TEST) Field Descriptions
533
ECC Test Register (FECC_TEST)
533
ECC Control Register (FECC_CTRL)
534
ECC Control Register (FECC_CTRL) Field Descriptions
534
ECC Test Register (FECC_TEST) Field Descriptions
534
Test Data out High Register (FECC_FOUTH_TEST)
534
Test Data out High Register (FECC_FOUTH_TEST) Field Descriptions
534
Test Data out Low Register (FECC_FOUTL_TEST)
534
ECC Status Register (FECC_STATUS)
535
ECC Status Register (FECC_STATUS) Field Descriptions
535
Test Data out Low Register (FECC_FOUTL_TEST) Field Descriptions
535
Master Subsystem Boot Mode Selection
538
Device Boot Flow
540
M-Boot ROM Memory Map
541
M-Boot ROM Vector Table
541
M-Boot ROM Version and Checksum Information
542
REV0 - User Configurable DCSM OTP Fields
543
REVA - User Configurable DCSM OTP Fields
543
M-Boot ROM Entry Points
544
M-Boot ROM Boot Mode GPIO Assignments
546
M-Boot ROM Clock Settings
546
M-Boot ROM Flow Diagram
550
M-Boot ROM Boot Status
552
M-Boot ROM Exceptions Handling
553
M-Boot ROM Reset Cause Handling
553
M-Boot ROM Serial Boot Commands
556
M-Boot ROM CAN Boot Commands
562
Overview of Parallel GPIO Bootloader Operation
564
Parallel GPIO Boot 8-Bit Data Stream
565
Parallel GPIO Bootloader Handshake Protocol
565
Parallel GPIO Mode Overview
566
Parallel GPIO Mode - Host Transfer Flow
567
8-Bit Parallel Getword Function
568
C-Boot ROM Memory Map
571
C-Boot ROM PIE Mismatch Handler
574
C-Boot ROM Version and Checksum Information
574
C-Boot ROM CPU Vector Table
575
C-Boot ROM Vector Table Map
575
PIE Vector Table in C-Boot ROM
576
C-Boot ROM Boot Modes
578
C-Boot ROM Entry Point
579
C-Boot ROM GPIO Assignments for Boot Modes
581
C-Boot ROM Flow Chart
583
Master Subsystem Application Procedure to Send IPC to C-Boot ROM
585
C-Boot ROM Handling on MTOCIPC
587
MTOC IPC Commands
588
C-Boot ROM NAK/ERROR Status Returns for MTOCIPCCOM
590
C-Boot ROM Boot Status Values
591
C-Boot ROM Health Status
591
CTOM IPC Messages
592
C-Boot ROM Exceptions Handling
593
General Structure of Source Program Data Stream in 16-Bit Mode
596
LSB/MSB Loading Sequence in 8-Bit Data Stream
598
Bootloader Basic Transfer Procedure
600
Overview of Copydata Function
601
Overview of SCI Bootloader Operation
601
Overview of Sci_Boot Function
602
Overview of Sci_Getworddata Function
603
SPI 8-Bit Data Stream
604
SPI Loader
604
Data Transfer from EEPROM Flow
606
Overview of Spia_Getworddata Function
606
EEPROM Device at Address 0X50
607
Overview of I2C_Boot Function
608
I2C 8-Bit Data Stream
609
Random Read
609
Sequential Read
609
Overview of Parallel GPIO Bootloader Operation
610
Parallel GPIO Boot 8-Bit Data Stream
611
Parallel GPIO Bootloader Handshake Protocol
611
Parallel GPIO Mode Overview
612
Parallel GPIO Mode - Host Transfer Flow
613
8-Bit Parallel Getword Function
614
Master Subsystem Application Flow to Start C-Boot ROM Loaders
615
Build a Binary Image for Bootload Using M-BOOT ROM
619
LM FLASH Programmer Configuration Screen
620
LM FLASH Programmer Interface Selection Screen
621
LM FLASH Programmer Serial Interface Configuration Screen
622
LM FLASH Programmer Binary Image Selection Screen
623
LM FLASH Programmer EMAC Interface Selection Screen
624
FLASH Programmer EMAC Bootload Binary Image Selection Screen
625
Bootloader Options
626
Multiple Epwm Modules
633
Submodules and Signal Connections for an Epwm Module
634
Epwm Submodules and Critical Internal Signal Interconnects
635
Epwm Module Control and Status Register Set Grouped by Submodule
637
Epwm Module Control and Status Register Set Grouped by Submodule (Upper Page)
639
Submodule Configuration Parameters
641
Time-Base Submodule
643
Time-Base Submodule Registers
644
Key Time-Base Signals
645
Time-Base Submodule Signals and Registers
645
Time-Base Frequency and Period
647
Time-Base Counter Synchronization Scheme 4
648
Time-Base Up-Count Mode Waveforms
651
Time-Base Down-Count Mode Waveforms
652
Time-Base Up-Down-Count Waveforms, TBCTL[PHSDIR = 0] Count down on Synchronization Event
652
Counter-Compare Submodule
653
Time-Base Up-Down Count Waveforms, TBCTL[PHSDIR = 1] Count up on Synchronization Event
653
Counter-Compare Submodule Registers
654
Counter-Compare Submodule Key Signals
655
Detailed View of the Counter-Compare Submodule
655
Counter-Compare Event Waveforms in Up-Count Mode
658
Counter-Compare Events in Down-Count Mode
659
Counter-Compare Events in Up-Down-Count Mode, TBCTL[PHSDIR = 0] Count down on Synchronization Event
660
Counter-Compare Events in Up-Down-Count Mode, TBCTL[PHSDIR = 1] Count up on Synchronization Event
660
Action-Qualifier Submodule
661
Action-Qualifier Submodule Registers
661
Action-Qualifier Submodule Inputs and Outputs
662
Action-Qualifier Submodule Possible Input Events
662
Possible Action-Qualifier Actions for Epwmxa and Epwmxb Outputs
663
Action-Qualifier Event Priority for Down-Count Mode
664
Action-Qualifier Event Priority for Up-Count Mode
664
Action-Qualifier Event Priority for Up-Down-Count Mode
664
Behavior if CMPA/CMPB Is Greater than the Period
664
Aqctlr[Shdwaqamode]
666
Aqctlr[Shdwaqbmode]
666
Up-Down-Count Mode Symmetrical Waveform
668
Up, Single Edge Asymmetric Waveform, with Independent Modulation on Epwmxa and Epwmxb-Active High
669
Up, Single Edge Asymmetric Waveform with Independent Modulation on Epwmxa and Epwmxb-Active Low
670
Up-Count, Pulse Placement Asymmetric Waveform with Independent Modulation on Epwmxa
671
Up-Down-Count, Dual Edge Symmetric Waveform, with Independent Modulation on Epwmxa and Epwmxb - Active Low
673
Up-Down-Count, Dual Edge Symmetric Waveform, with Independent Modulation on Epwmxa and Epwmxb - Complementary
674
Up-Down-Count, Dual Edge Asymmetric Waveform, with Independent Modulation on Epwmxa-Active Low
675
Dead_Band Submodule
676
Dead-Band Generator Submodule Registers
678
Classical Dead-Band Operating Modes
679
Configuration Options for the Dead-Band Submodule
679
Additional Dead-Band Operating Modes
680
Dead-Band Waveforms for Typical Cases (0% < Duty < 100%)
681
Dead-Band Delay Values in Μs as a Function of DBFED and DBRED
682
PWM-Chopper Submodule
683
PWM-Chopper Submodule Registers
683
PWM-Chopper Submodule Operational Details
684
Simple PWM-Chopper Submodule Waveforms Showing Chopping Action Only
684
Possible Pulse Width Values for SYSCLKOUT = 80 Mhz
685
PWM-Chopper Submodule Waveforms Showing the First Pulse and Subsequent Sustaining Pulses
685
PWM-Chopper Submodule Waveforms Showing the Pulse Width (Duty Cycle) Control of Sustaining Pulses
686
Trip-Zone Submodule
687
Trip-Zone Submodule Registers
688
Possible Actions on a Trip Event
690
Trip-Zone Submodule Mode Control Logic
691
Trip-Zone Submodule Interrupt Logic
692
Event-Trigger Submodule
693
Trigxsel Trigger Options
693
Event-Trigger Submodule Inter-Connectivity of ADC Start of Conversion
694
Event-Trigger Submodule Registers
695
Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs
695
Event-Trigger Interrupt Generator
697
Event-Trigger SOCA Pulse Generator
698
Event-Trigger SOCB Pulse Generator
698
Digital-Compare Submodule High-Level Block Diagram
699
GPIO MUX-To-Trip Input Connectivity
700
Digital Compare Submodule Registers
701
DCAEVT1 Event Triggering
703
DCAEVT2 Event Triggering
703
DCBEVT1 Event Triggering
704
DCBEVT2 Event Triggering
704
Event Filtering
705
Blanking Window Timing Diagram
706
Simplified Epwm Module
707
EPWM1 Configured as a Typical Master, EPWM2 Configured as a Slave
708
Control of Four Buck Stages. here F
709
Pwm1 Pwm2 Pwm3 Pwm4
709
Pwm1 ≠ F
709
Buck Waveforms for (Note: Only Three Bucks Shown Here)
710
Control of Four Buck Stages
712
Pwm1 )
712
Pwm2 Pwm1
712
Pwm1) )
713
Pwm2 Pwm1
713
Control of Dual 3-Phase Inverter Stages as Is Commonly Used in Motor Control
718
3-Phase Inverter Waveforms for (Only One Inverter Shown)
719
Configuring Two PWM Modules for Phase Control
721
Timing Waveforms Associated with Phase Control between 2 Modules
722
Control of a 3-Phase Interleaved DC/DC Converter
723
3-Phase Interleaved DC/DC Converter Waveforms for
724
Controlling a Full-H Bridge Stage
726
Pwm2 Pwm1)
726
ZVS Full-H Bridge Waveforms
727
Peak Current Mode Control of a Buck Converter
729
Peak Current Mode Control Waveforms for
729
Control of Two Resonant Converter Stages
731
H-Bridge LLC Resonant Converter PWM Waveforms
731
Time-Base Period and Mirror 2 Register (TBPRD / TBPRDM2)
733
Time-Base Period and Mirror 2 Register (TBPRD / TBPRDM2) Field Descriptions
733
Time-Base Period High-Resolution and Mirror 2 Register (TBPRDHR / TBPRDHRM2)
733
Time-Base Period High-Resolution and Mirror 2 Register (TBPRDHR / TBPRDHRM2) Field Descriptions
733
Time-Base Period Mirror Register (TBPRDM)
733
Time-Base Period High-Resolution Mirror Register (TBPRDHRM)
734
Time-Base Period High-Resolution Mirror Register (TBPRDHRM) Field Descriptions
734
Time-Base Period Mirror Register (TBPRDM) Field Descriptions
734
Time-Base Phase Register and Mirror Register (TBPHS / TBPHSM)
734
Time-Base Control Register (TBCTL)
735
Time-Base Counter Register (TBCTR)
735
Time-Base Counter Register (TBCTR) Field Descriptions
735
Time-Base Phase High-Resolution Register and Mirror Register (TBPHSHR / TBPHSHRM)
735
Time-Base Phase High-Resolution Register and Mirror Register (TBPHSHR / TBPHSHRM) Field Descriptions
735
Time-Base Phase Register and Mirror Register (TBPHS / TBPHSM) Field Descriptions
735
Time-Base Control Register (TBCTL) Field Descriptions
736
High-Resolution Period Control Register (HRPCTL)
738
High-Resolution Period Control Register (HRPCTL) Field Descriptions
738
Time-Base Status Register (TBSTS)
738
Time-Base Status Register (TBSTS) Field Descriptions
738
Epwmx Link Register (EPWMXLINK)
739
Time-Base Control Register 2 (TBCTL2)
739
Time-Base Control Register 2 (TBCTL2) Field Descriptions
739
Epwmx Link Register (EPWMXLINK) Field Descriptions
740
Counter-Compare Control Register (CMPCTL)
742
Counter-Compare Control Register (CMPCTL) Field Descriptions
742
Compare Control Register (CMPCTL2)
743
Counter-Compare Control Register (CMPCTL2) Field Descriptions
743
Compare a High-Resolution and Mirror 2 Register (CMPAHR / CMPAHRM2 )
744
Compare a High-Resolution and Mirror 2 Register (CMPAHR / CMPAHRM2 ) Field Descriptions
744
Compare a High-Resolution Mirror Register (CMPAHRM)
745
Compare a High-Resolution Mirror Register (CMPAHRM) Field Descriptions
745
Counter-Compare a and Mirror 2 Register (CMPA / CMPAM2)
745
Counter-Compare a and Mirror 2 Register (CMPA / CMPAM2) Field Descriptions
745
Counter-Compare a Mirror Register (CMPAM)
745
Counter-Compare a Mirror Register (CMPAM) Field Descriptions
746
Counter-Compare B Register (CMPB)
746
Counter-Compare B Register (CMPBM)
746
Counter-Compare B Register (CMPBM) Field Descriptions
746
Counter-Compare B Register (CMPB) Field Descriptions
747
Counter-Compare C Register (CMPC)
747
Counter-Compare C Register (CMPC) Field Descriptions
747
Counter-Compare D Register (CMPD)
747
Compare B High-Resolution Mirror Register (CMPBHRM)
748
Compare B High-Resolution Mirror Register (CMPBHRM) Field Descriptions
748
Compare B High-Resolution Register (CMPBHR)
748
Compare B High-Resolution Register (CMPBHR) Field Descriptions
748
Counter-Compare D Register (CMPD) Field Descriptions
748
Action-Qualifier Output a Control Register and Mirror Register (AQCTLA / AQCTLAM)
749
Action-Qualifier Output a Control Register and Mirror Register (AQCTLA / AQCTLAM) Field Descriptions
749
Action-Qualifier Output B Control Register and Mirror Register (AQCTLB / AQCTLBM)
750
Action-Qualifier Output B Control Register and Mirror Register (AQCTLB / AQCTLBM) Field Descriptions
750
Action-Qualifier Software Force Register and Mirror Register (AQSFRC / AQSFRCM)
751
Action-Qualifier Software Force Register and Mirror Register (AQSFRC / AQSFRCM) Field Descriptions
751
Action-Qualifier Continuous Software Force Register and Mirror Register (AQCSFRC / AQCSFRCM)
752
Action-Qualifier Continuous Software Force Register and Mirror Register (AQCSFRC / AQCSFRCM) Field Descriptions
752
Action Qualifier Control Register (AQCTLR)
753
Action Qualifier Control Register (AQCTLR) Field Description
753
Dead-Band Generator Control Register (DBCTL)
754
Dead-Band Generator Control Register (DBCTL) Field Descriptions
754
Dead Band Falling Edge Delay High-Resolution Register (DBFEDHR)
756
Dead Band Rising Edge Delay High-Resolution Register (DBREDHR)
756
Dead Band Rising Edge Delay High-Resolution Register (DBREDHR) Field Descriptions
756
Dead-Band Generator Falling Edge Delay and Mirror Register (DBFED / DBFEDM)
756
Dead-Band Generator Falling Edge Delay and Mirror Register (DBFED / DBFEDM) Field Descriptions
756
Dead-Band Generator Rising Edge Delay and Mirror Register (DBRED / DBREDM)
756
Dead-Band Generator Rising Edge Delay and Mirror Register (DBRED / DBREDM) Field Descriptions
756
Dead Band Falling Edge Delay High-Resolution Register (DBFEDHR) Field Descriptions
757
PWM-Chopper Control Register (PCCTL)
758
PWM-Chopper Control Register (PCCTL) Bit Descriptions
758
Trip-Zone Select Register (TZSEL)
760
Trip-Zone Submodule Select Register (TZSEL) Field Descriptions
760
Trip-Zone Control Register (TZCTL)
761
Trip-Zone Control Register Field Descriptions
761
Trip-Zone Enable Interrupt Register (TZEINT)
762
Trip-Zone Enable Interrupt Register (TZEINT) Field Descriptions
762
Trip-Zone Flag Register (TZFLG)
763
Trip-Zone Flag Register (TZFLG) Field Descriptions
763
Trip-Zone Clear Register and Mirror Register (TZCLR / TZCLRM)
764
Trip-Zone Clear Register and Mirror Register (TZCLR / TZCLRM) Field Descriptions
764
Trip-Zone Digital Compare Event Select Register (TZDCSEL)
765
Trip-Zone Force Register (TZFRC)
765
Trip-Zone Force Register (TZFRC) Field Descriptions
765
Trip Zone Digital Compare Event Select Register (TZDCSEL) Field Descriptions
766
Digital Compare Trip Select (DCTRIPSEL)
767
Digital Compare Trip Select (DCTRIPSEL) Field Descriptions
767
Digital Compare a Control Register (DCACTL)
768
Digital Compare a Control Register (DCACTL) Field Descriptions
768
Digital Compare B Control Register (DCBCTL)
769
Digital Compare B Control Register (DCBCTL) Field Descriptions
769
Digital Compare Filter Control Register (DCFCTL)
769
Digital Compare Filter Control Register (DCFCTL) Field Descriptions
769
Digital Compare Capture Control Register (DCCAPCTL)
770
Digital Compare Capture Control Register (DCCAPCTL) Field Descriptions
770
Digital Compare Counter Capture Register (DCCAP)
770
Digital Compare Counter Capture Register (DCCAP) Field Descriptions
771
Digital Compare Filter Offset Counter Register (DCFOFFSETCNT)
771
Digital Compare Filter Offset Counter Register (DCFOFFSETCNT) Field Descriptions
771
Digital Compare Filter Offset Register (DCFOFFSET)
771
Digital Compare Filter Offset Register (DCFOFFSET) Field Descriptions
771
Digital Compare a High Trip Input Select (DCAHTRIPSEL) (EALLOW-Protected)
772
Digital Compare Filter Window Counter Register (DCFWINDOWCNT)
772
Digital Compare Filter Window Counter Register (DCFWINDOWCNT) Field Descriptions
772
Digital Compare Filter Window Register (DCFWINDOW)
772
Digital Compare Filter Window Register (DCFWINDOW) Field Descriptions
772
Digital Compare a High Trip Input Select (DCAHTRIPSEL) Field Descriptions
773
Digital Compare a Low Trip Input Select (DCALTRIPSEL) (EALLOW-Protected)
774
Digital Compare a Low Trip Input Select (DCALTRIPSEL) Field Descriptions
774
Digital Compare B High Trip Input Select (DCBHTRIPSEL) (EALLOW-Protected)
775
Digital Compare B High Trip Input Select (DCBHTRIPSEL) Field Descriptions
775
Digital Compare B Low Trip Input Select (DCBLTRIPSEL) (EALLOW-Protected)
776
Digital Compare B Low Trip Input Select (DCBLTRIPSEL) Field Descriptions
776
GPIO Trip Input Select Register (Gptripxsel)
778
GPIOTRIP Input Select Registers
778
GPTRIP Input Signals
778
GPIO Trip Input Select Register (Gptripxsel) Field Descriptions
779
Event-Trigger Selection Register (ETSEL)
780
Event-Trigger Selection Register (ETSEL) Field Descriptions
780
Event-Trigger Prescale Register (ETPS)
781
Event-Trigger Prescale Register (ETPS) Field Descriptions
782
Event-Trigger Interrupt Pre-Scale Register (ETINTPS)
783
Event-Trigger Interrupt Pre-Scale Register (ETINTPS) Field Descriptions
783
Event-Trigger SOC Pre-Scale Register (ETSOCPS)
784
Event-Trigger SOC Pre-Scale Register (ETSOCPS) Field Descriptions
784
Event-Trigger Flag Register (ETFLG)
785
Event-Trigger Flag Register (ETFLG) Field Descriptions
785
Event-Trigger Clear Register and Mirror Register (ETCLR / ETCLRM)
786
Event-Trigger Clear Register and Mirror Register (ETCLR / ETCLRM) Field Descriptions
786
Event-Trigger Force Register (ETFRC)
786
Event-Trigger Force Register (ETFRC) Field Descriptions
786
Event-Trigger Counter Initialization Control Register (ETCNTINITCTL)
787
Event-Trigger Counter Initialization Control Register (ETCNTINITCTL) Field Descriptions
787
Event-Trigger Counter Initialization Register (ETCNTINIT)
787
Event-Trigger Counter Initialization Register (ETCNTINIT) Field Descriptions
788
Capture and APWM Modes of Operation
792
Counter Compare and PRD Effects on the Ecap Output in APWM Mode
793
Capture Function Diagram
794
Event Prescale Control
795
Prescale Function Waveforms
795
Details of the Continuous/One-Shot Block
796
Details of the Counter and Synchronization Block
797
Interrupts in Ecap Module
798
PWM Waveform Details of APWM Mode Operation
799
Time-Base Frequency and Period Calculation
800
Capture-1 Register (CAP1)
801
Capture-1 Register (CAP1) Field Descriptions
801
Capture-2 Register (CAP2)
801
Capture-2 Register (CAP2) Field Descriptions
801
Counter Phase Control Register (CTRPHS)
801
Counter Phase Control Register (CTRPHS) Field Descriptions
801
Time-Stamp Counter Register (TSCTR)
801
Time-Stamp Counter Register (TSCTR) Field Descriptions
801
Capture-3 Register (CAP3)
802
Capture-3 Register (CAP3) Field Descriptions
802
Capture-4 Register (CAP4)
802
Capture-4 Register (CAP4) Field Descriptions
802
ECAP Control Register 1 (ECCTL1)
802
ECAP Control Register 1 (ECCTL1) Field Descriptions
802
ECAP Control Register 2 (ECCTL2)
803
ECAP Control Register 2 (ECCTL2) Field Descriptions
804
ECAP Interrupt Enable Register (ECEINT)
806
ECAP Interrupt Enable Register (ECEINT) Field Descriptions
806
ECAP Interrupt Clear Register (ECCLR)
807
ECAP Interrupt Flag Register (ECFLG)
807
ECAP Interrupt Flag Register (ECFLG) Field Descriptions
807
ECAP Interrupt Clear Register (ECCLR) Field Descriptions
808
ECAP Interrupt Forcing Register (ECFRC)
808
ECAP Interrupt Forcing Register (ECFRC) Field Descriptions
808
Control and Status Register Set
809
Capture Sequence for Absolute Time-Stamp and Rising Edge Detect
810
Capture Sequence for Absolute Time-Stamp with Rising and Falling Edge Detect
812
Capture Sequence for Delta Mode Time-Stamp and Rising Edge Detect
814
Capture Sequence for Delta Mode Time-Stamp with Rising and Falling Edge Detect
816
PWM Waveform Details of APWM Mode Operation
818
Optical Encoder Disk
821
QEP Encoder Output Signal for Forward/Reverse Movement
821
Index Pulse Example
822
EQEP Memory Map
824
Functional Block Diagram of the Eqep Peripheral
824
Functional Block Diagram of Decoder Unit
826
Quadrature Decoder State Machine
827
Quadrature Decoder Truth Table
827
Quadrature-Clock and Direction Decoding
828
Position Counter Reset by Index Pulse for 1000 Line Encoder (QPOSMAX = 3999 or 0Xf9F)
830
Position Counter Underflow/Overflow (QPOSMAX = 4)
831
Software Index Marker for 1000-Line Encoder (QEPCTL[IEL] = 1)
832
Strobe Event Latch (QEPCTL[SEL] = 1)
833
Eqep Position-Compare Unit
834
Eqep Position-Compare Event Generation Points
835
Eqep Position-Compare Sync Output Pulse Stretcher
835
Eqep Edge Capture Unit
837
Unit Position Event for Low Speed Measurement (QCAPCTL[UPPS] = 0010)
837
Eqep Edge Capture Unit - Timing Details
838
Eqep Unit Time Base
839
Eqep Watchdog Timer
839
Eqep Decoder Control (QDECCTL) Register Field Descriptions
840
EQEP Interrupt Generation
840
QEP Decoder Control (QDECCTL) Register
840
Eqep Control (QEPCTL) Register
841
Eqep Control (QEPCTL) Register Field Descriptions
842
Eqep Position-Compare Control (QPOSCTL) Register
843
Eqep Position-Compare Control (QPOSCTL) Register Field Descriptions
843
Eqep Capture Control (QCAPCTL) Register
844
Eqep Capture Control (QCAPCTL) Register Field Descriptions
844
Eqep Position Counter (QPOSCNT) Register
844
Eqep Position Counter (QPOSCNT) Register Field Descriptions
844
Eqep Position Counter Initialization (QPOSINIT) Register
844
Eqep Index Position Latch (QPOSILAT) Register
845
Eqep Index Position Latch (QPOSILAT) Register Field Descriptions
845
Eqep Maximum Position Count (QPOSMAX) Register Field Descriptions
845
Eqep Maximum Position Count Register (QPOSMAX) Register
845
Eqep Position Counter Initialization (QPOSINIT) Register Field Descriptions
845
Eqep Position-Compare (QPOSCMP) Register
845
Eqep Position-Compare (QPOSCMP) Register Field Descriptions
845
Eqep Strobe Position Latch (QPOSSLAT) Register
845
Eqep Position Counter Latch (QPOSLAT) Register
846
Eqep Position Counter Latch (QPOSLAT) Register Field Descriptions
846
Eqep Register Unit Period (QUPRD) Register
846
Eqep Strobe Position Latch (QPOSSLAT) Register Field Descriptions
846
Eqep Unit Period (QUPRD) Register Field Descriptions
846
Eqep Unit Timer (QUTMR) Register
846
Eqep Unit Timer (QUTMR) Register Field Descriptions
846
Eqep Watchdog Timer (QWDTMR) Register
846
Eqep Interrupt Enable (QEINT) Register
847
Eqep Interrupt Enable(QEINT) Register Field Descriptions
847
Eqep Watchdog Period (QWDPRD) Register
847
Eqep Watchdog Period (QWDPRD) Register Field Description
847
Eqep Watchdog Timer (QWDTMR) Register Field Descriptions
847
Eqep Interrupt Flag (QFLG) Register
848
Eqep Interrupt Flag (QFLG) Register Field Descriptions
848
Eqep Interrupt Clear (QCLR) Register
849
Eqep Interrupt Clear (QCLR) Register Field Descriptions
849
Eqep Interrupt Force (QFRC) Register
850
Eqep Interrupt Force (QFRC) Register Field Descriptions
850
Eqep Status (QEPSTS) Register
851
Eqep Status (QEPSTS) Register Field Descriptions
851
Eqep Capture Period (QCPRD) Register
852
Eqep Capture Period Register (QCPRD) Register Field Descriptions
852
Eqep Capture Timer (QCTMR) Register
852
Eqep Capture Timer (QCTMR) Register Field Descriptions
852
Eqep Capture Timer Latch (QCTMRLAT) Register
852
Eqep Capture Period Latch (QCPRDLAT) Register
853
Eqep Capture Period Latch (QCPRDLAT) Register Field Descriptions
853
Eqep Capture Timer Latch (QCTMRLAT) Register Field Descriptions
853
Analog Subsystem Block Diagram
855
Simplified ACIB Model
856
Simplified ACIB Signals
856
16-Bit Read
857
16-Bit Write
857
32-Bit Read
858
ADC Trigger
858
ADC Interrupt
859
ADC Module Block Diagram
860
SOC Block Diagram
861
Trigxsel Trigger Options
862
Adcinx Input Model
863
Sample Timings with Different Values of ACQPS
863
ONESHOT Single Conversion
864
Round Robin Priority Example
866
High Priority Example
867
Interrupt Structure
869
ADC Configuration and Control Registers (Adcregs and Adcresult)
872
ADC Registers
872
ADC Control Register 1 (ADCCTL1) (Address Offset 00H)
873
ADC Control Register 1 (ADCCTL1) Field Descriptions
873
ADC Control Register 2 (ADCCTL2) (Address Offset 01H)
875
ADC Control Register 2 (ADCCTL2) Field Descriptions
875
ADC Interrupt Flag Register (ADCINTFLG) (Address Offset 04H)
875
ADC Interrupt Flag Register (ADCINTFLG) Field Descriptions
875
ADC Interrupt Flag Clear Register (ADCINTFLGCLR) (Address Offset 05H)
876
ADC Interrupt Flag Clear Register (ADCINTFLGCLR) Field Descriptions
876
ADC Interrupt Overflow Clear Register (ADCINTOVFCLR) (Address Offset 07H)
876
ADC Interrupt Overflow Register (ADCINTOVF) (Address Offset 06H)
876
ADC Interrupt Overflow Register (ADCINTOVF) Field Descriptions
876
ADC Interrupt Overflow Clear Register (ADCINTOVFCLR) Field Descriptions
877
Interrupt Select 1 and 2 Register (INTSEL1N2) (Address Offset 08H)
877
Interrupt Select 3 and 4 Register (INTSEL3N4) (Address Offset 09H)
877
Interrupt Select 5 and 6 Register (INTSEL5N6) (Address Offset 0Ah)
877
Interrupt Select 7 and 8 Register (INTSEL7N8) (Address Offset 0Bh)
877
Interrupt Select 9 and 10 Register (INTSEL9N10) (Address Offset 0Ch)
878
Intselxny Register Field Descriptions
878
ADC Start of Conversion Priority Control Register (SOCPRICTL)
879
SOCPRICTL Register Field Descriptions
879
ADC Sample Mode Register (ADCSAMPLEMODE) (Address Offset 12H)
881
ADC Sample Mode Register (ADCSAMPLEMODE) Field Descriptions
881
ADC Interrupt Trigger SOC Select 1 Register (ADCINTSOCSEL1) (Address Offset 14H)
882
ADC Interrupt Trigger SOC Select 1 Register (ADCINTSOCSEL1) Register Field Descriptions
882
ADC Interrupt Trigger SOC Select 2 Register (ADCINTSOCSEL2) (Address Offset 15H)
883
ADC Interrupt Trigger SOC Select 2 Register (ADCINTSOCSEL2) Field Descriptions
883
ADC SOC Flag 1 Register (ADCSOCFLG1) (Address Offset 18H)
883
ADC SOC Flag 1 Register (ADCSOCFLG1) Field Descriptions
883
ADC SOC Force 1 Register (ADCSOCFRC1) (Address Offset 1Ah)
883
ADC SOC Force 1 Register (ADCSOCFRC1) Field Descriptions
884
ADC SOC Overflow 1 Register (ADCSOCOVF1) (Address Offset 1Ch)
884
ADC SOC Overflow 1 Register (ADCSOCOVF1) Field Descriptions
884
ADC SOC Overflow Clear 1 Register (ADCSOCOVFCLR1) (Address Offset 1Eh)
884
ADC SOC Overflow Clear 1 Register (ADCSOCOVFCLR1) Field Descriptions
884
ADC SOC0 - SOC15 Control Registers (Adcsocxctl) (Address Offset 20H - 2Fh)
885
ADC SOC0 - SOC15 Control Registers (Adcsocxctl) Register Field Descriptions
885
ADC Offset Trim Register (ADCOFFTRIM) (Address Offset 41H)
887
ADC Reference/Gain Trim Register (ADCREFTRIM) (Address Offset 40H)
887
ADC Reference/Gain Trim Register (ADCREFTRIM) Field Descriptions
887
ADC Offset Trim Register (ADCOFFTRIM) Field Descriptions
888
ADC RESULT0 - ADCRESULT15 Registers (Adcresultx) Field Descriptions
888
ADC RESULT0 - RESULT15 Registers (Adcresultx) (PF1 Block Address Offset 00H - 0Fh)
888
ADC Revision Register (ADCREV) (Address Offset 4Fh)
888
ADC Revision Register (ADCREV) Field Descriptions
888
Analog Subsystem Control Registers (Analogsysctrlreg)
889
ADC Interrupt Overflow Detect Register (INTOVF)
890
ADC Interrupt Overflow Detect Register (INTOVF) Field Descriptions
890
ADC Interrupt Overflow Clear Register (INTOVFCLR)
891
ADC Interrupt Overflow Clear Register (INTOVFCLR) Field Descriptions
891
Control System: Lock Register (CLOCK)
892
Control System: Lock Register (CLOCK) Field Descriptions
892
Control System: ACIB Status Register (CCIBSTATUS)
893
Control System: ACIB Status Register (CCIBSTATUS) Field Descriptions
893
Control System: Clock Control Register (CCLKCTL)
894
Control System: Clock Control Register (CCLKCTL) Field Descriptions
894
ADC Start of Conversion Trigger Overflow Detect Register (TRIGOVF)
895
ADC Start of Conversion Trigger Overflow Detect Register (TRIGOVF) Field Descriptions
895
ADC Start of Conversion Trigger Overflow Flag Clear Register (TRIGOVFCLR)
896
ADC Start of Conversion Trigger Overflow Flag Clear Register (TRIGOVFCLR) Field Descriptions
896
ADC Start of Conversion Trigx Input Select Register (Trigxsel)
897
ADC Start of Conversion Trigx Input Select Register (Trigxsel) Field Descriptions
897
Timing Example for Sequential Mode / Late Interrupt Pulse
898
Timing Example for Sequential Mode / Early Interrupt Pulse
899
Timing Example for Simultaneous Mode / Late Interrupt Pulse
900
Timing Example for Simultaneous Mode / Early Interrupt Pulse
901
Comparator
902
Comparator Block Diagram
902
Comparator Truth Table
902
Comparator Control (COMPCTL) Register
904
Comparator Module Registers
904
COMPCTL Register Field Descriptions
904
Compare Output Status (COMPSTS) Register
905
Compare Output Status (COMPSTS) Register Field Descriptions
905
DAC Value (DACVAL) Register
905
DAC Value (DACVAL) Register Field Descriptions
905
DAC Test (DACTEST) Register
906
DAC Test (DACTEST) Register Field Descriptions
906
DMA Block Diagram
913
Peripheral Interrupt Trigger Input Diagram
914
Peripheral Interrupt Trigger Source Options
915
4-Stage Pipeline DMA Transfer
916
4-Stage Pipeline with One Read Stall (Mcbsp as Source)
916
Arbitration When Accessing ACIB
918
DMA State Diagram
923
Overrun Detection Logic
925
DMA Register Summary
926
DMA Control Register (DMACTRL)
927
DMA Control Register (DMACTRL) Field Descriptions
927
Debug Control Register (DEBUGCTRL)
929
Debug Control Register (DEBUGCTRL) Field Descriptions
929
Revision Register (REVISION)
929
Revision Register (REVISION) Field Descriptions
929
Priority Control Register 1 (PRIORITYCTRL1)
930
Priority Control Register 1 (PRIORITYCTRL1) Field Descriptions
930
Priority Status Register (PRIORITYSTAT)
931
Priority Status Register (PRIORITYSTAT) Field Descriptions
931
Mode Register (MODE)
932
Mode Register (MODE) Field Descriptions
932
Control Register (CONTROL)
934
Control Register (CONTROL) Field Descriptions
934
Burst Count Register (BURST_COUNT)
936
Burst Count Register (BURST_COUNT) Field Descriptions
936
Burst Size Register (BURST_SIZE)
936
Burst Size Register (BURST_SIZE) Field Descriptions
936
Source Burst Step Size Register (SRC_BURST_STEP)
937
Source Burst Step Size Register (SRC_BURST_STEP) Field Descriptions
937
Destination Burst Step Register Size (DST_BURST_STEP)
938
Destination Burst Step Register Size (DST_BURST_STEP) Field Descriptions
938
Transfer Size Register (TRANSFER_SIZE)
938
Transfer Size Register (TRANSFER_SIZE) Field Descriptions
938
Source Transfer Step Size Register (SRC_TRANSFER_STEP)
939
Source Transfer Step Size Register (SRC_TRANSFER_STEP) Field Descriptions
939
Transfer Count Register (TRANSFER_COUNT)
939
Transfer Count Register (TRANSFER_COUNT) Field Descriptions
939
Destination Transfer Step Size Register (DST_TRANSFER_STEP)
940
Destination Transfer Step Size Register (DST_TRANSFER_STEP) Field Descriptions
940
Source/Destination Wrap Size Register (SRC/DST_WRAP_SIZE)
940
Source/Destination Wrap Size Register (SRC/DST_WRAP_SIZE) Field Descriptions
940
Source/Destination Wrap Count Register (SCR/DST_WRAP_COUNT)
941
Source/Destination Wrap Count Register (SCR/DST_WRAP_COUNT) Field Descriptions
941
Source/Destination Wrap Step Size Registers (SRC/DST_WRAP_STEP)
941
Source/Destination Wrap Step Size Registers (SRC/DST_WRAP_STEP) - EALLOW Protected
941
Source/Destination Wrap Step Size Registers (SRC/DST_WRAP_STEP) Field Descriptions
941
(Src_Beg_Addr/Dst_Beg_Addr)
942
(Src_Beg_Addr_Shadow/Dst_Beg_Addr_Shadow)
942
Active Source Begin and Current Address Pointer Registers
942
Active Source Begin and Current Address Pointer Registers (SRC_BEG_ADDR/DST_BEG_ADDR)
942
Active Source Begin and Current Address Pointer Registers (SRC_BEG_ADDR/DST_BEG_ADDR) Field
942
Descriptions
942
Shadow Source Begin and Current Address Pointer Registers
942
Shadow Source Begin and Current Address Pointer Registers (SRC_BEG_ADDR_SHADOW/DST_BEG_ADDR_SHADOW) - All EALLOW Protected
942
Shadow Source Begin and Current Address Pointer Registers (SRC_BEG_ADDR_SHADOW/DST_BEG_ADDR_SHADOW) Field Descriptions
942
(Src_Addr_Shadow/Dst_Addr_Shadow)
943
(SRC_ADDR_SHADOW/DST_ADDR_SHADOW) Field Descriptions
943
Active Destination Begin and Current Address Pointer Registers (SRC_ADDR/DST_ADDR)
943
Active Destination Begin and Current Address Pointer Registers (SRC_ADDR/DST_ADDR) Field
943
Descriptions
943
Shadow Destination Begin and Current Address Pointer Registers
943
Shadow Destination Begin and Current Address Pointer Registers (SRC_ADDR_SHADOW/DST_ADDR_SHADOW) - All EALLOW Protected
943
C28 Serial Peripheral Interface (SPI)
944
Enhanced SPI Module Overview
945
SPI CPU Interface
945
SPI Block Diagram
946
Serial Peripheral Interface Module Block Diagram
947
Overview of SPI Module Registers
948
SPI Module Signal Summary
948
SPI Registers
948
SPI Operation
949
SPI Master/Slave Connection
950
SPI Interrupts
951
SPI Clocking Scheme Selection Guide
954
SPI: SPICLK-CLKOUT Characteristic When (BRR + 1) Is Odd, BRR > 3, and CLOCK POLARITY = 1
954
SPICLK Signal Options
954
Five Bits Per Character
956
SPI FIFO Description
956
SPI FIFO Interrupt Flags and Enable Logic Generation
957
SPI Interrupt Flag Modes
957
4-Wire Vs. 3-Wire SPI Pin Functions
958
SPI 3-Wire Master Mode
958
SPI 3-Wire Mode Description
958
3-Wire SPI Pin Configuration
959
SPI 3-Wire Slave Mode
959
SPI STEINV Bit in Digital Audio Transfers
960
C28 SPI-A to M3 SSI3 Internal Loopback
961
SPI Digital Audio Receiver Configuration Using 2 Spis
961
Standard Right-Justified Digital Audio Data Format
961
Loopback Initialization and Configuration
962
Loopback Modes
962
SSI and SPI Connections for Loopback Mode
962
SPI Configuration Control Register (SPICCR) - Address 7040H
964
SPI Configuration Control Register (SPICCR) Field Descriptions
964
SPI Control Registers
964
SPI Registers and Waveforms
964
Character Length Control Bit Values
965
SPI Operation Control Register (SPICTL) - Address 7041H
965
SPI Operation Control Register (SPICTL) Field Descriptions
965
SPI Status Register (SPIST) - Address 7042H
966
SPI Status Register (SPIST) Field Descriptions
966
Field Descriptions
967
SPI Baud Rate Register (SPIBRR) - Address 7044H
967
SPI Emulation Buffer Register (SPIRXEMU) - Address 7046H
968
SPI Emulation Buffer Register (SPIRXEMU) Field Descriptions
968
SPI Serial Receive Buffer Register (SPIRXBUF) - Address 7047H
968
SPI Serial Receive Buffer Register (SPIRXBUF) Field Descriptions
968
SPI Serial Data Register (SPIDAT) - Address 7049H
969
SPI Serial Data Register (SPIDAT) Field Descriptions
969
SPI Serial Transmit Buffer Register (SPITXBUF) - Address 7048H
969
SPI Serial Transmit Buffer Register (SPITXBUF) Field Descriptions
969
SPI FIFO Receive (SPIFFRX) Register − Address 704Bh
970
SPI FIFO Transmit (SPIFFTX) Register Field Descriptions
970
SPI FIFO Transmit (SPIFFTX) Register − Address 704Ah
970
SPI FIFO Control (SPIFFCT) Register Field Descriptions
971
SPI FIFO Control (SPIFFCT) Register − Address 704Ch
971
SPI FIFO Receive (SPIFFRX) Register Field Descriptions
971
SPI Priority Control Register (SPIPRI) - Address 704Fh
972
SPI Priority Control Register (SPIPRI) Field Descriptions
972
Clock Polarity = 0, Clock Phase
973
CLOCK POLARITY = 0, CLOCK PHASE = 0 (All Data Transitions Are During the Rising Edge, Non-Delayed Clock. Inactive Level Is Low.)
973
SPI Example Waveforms
973
By Half Clock Cycle. Inactive Level Is Low.)
974
Clock Polarity = 1, Clock Phase
975
Level Is High.)
975
By Half Clock Cycle. Inactive Level Is High.)
976
Clock Polarity = 1, Clock Phase
976
SPISTE Behavior in Master Mode (Master Lowers SPISTE During the Entire 16 Bits of Transmission.)
977
SPISTE Behavior in Slave Mode (Slave's SPISTE Is Lowered During the Entire 16 Bits of Transmission.)
978
C28 Serial Communications Interface (SCI)
979
Enhanced SCI Module Overview
980
SCI CPU Interface
980
Serial Communications Interface (SCI) Module Block Diagram
981
Architecture
982
SCI-A Registers
982
SCI-B Registers
982
SCI Module Signal Summary
983
Programming the Data Format Using SCICCR
984
Typical SCI Data Frame Formats
984
Idle-Line Multiprocessor Communication Format
985
Double-Buffered WUT and TXSHF
986
Address-Bit Multiprocessor Communication Format
987
SCI Asynchronous Communications Format
988
SCI RX Signals in Communication Modes
988
SCI TX Signals in Communications Mode
989
Asynchronous Baud Register Values for Common SCI Bit Rates
990
SCI FIFO Interrupt Flags and Enable Logic
991
SCI Interrupt Flags
991
C28 SCI-A to M3 UART4 Internal Loopback
992
Loopback Initialization and Configuration
993
UART and SCI Connections for Loopback Mode
993
SCI Module Register Summary
994
SCI Registers
994
SCIA Registers
994
SCIB Registers
994
SCI Communication Control Register (SCICCR)
995
SCI Communication Control Register (SCICCR) - Address 7050H
995
SCI Communication Control Register (SCICCR) Field Descriptions
995
SCI Control Register 1 (SCICTL1)
996
SCI Control Register 1 (SCICTL1) - Address 7051H
996
SCI Control Register 1 (SCICTL1) Field Descriptions
996
Baud-Select Lsbyte Register (SCILBAUD) - Address 7053H
998
Baud-Select Msbyte Register (SCIHBAUD) - Address 7052H
998
Baud-Select Register Field Descriptions
998
SCI Baud-Select Registers (SCIHBAUD, SCILBAUD)
998
SCI Control Register 2 (SCICTL2)
999
SCI Control Register 2 (SCICTL2) - Address 7054H
999
SCI Control Register 2 (SCICTL2) Field Descriptions
999
SCI Receiver Status Register (SCIRXST)
999
SCI Receiver Status Register (SCIRXST) - Address 7055H
999
SCI Receiver Status Register (SCIRXST) Field Descriptions
1000
Emulation Data Buffer Register (SCIRXEMU) - Address 7056H
1001
Receiver Data Buffer Registers (SCIRXEMU, SCIRXBUF)
1001
Register SCIRXST Bit Associations - Address 7055H
1001
SCI Receive Data Buffer Register (SCIRXBUF) - Address 7057H
1001
SCI FIFO Registers (SCIFFTX, SCIFFRX, SCIFFCT)
1002
SCI FIFO Transmit (SCIFFTX) Register - Address 705Ah
1002
SCI FIFO Transmit (SCIFFTX) Register Field Descriptions
1002
SCI Receive Data Buffer Register (SCIRXBUF) Field Descriptions
1002
SCI Transmit Data Buffer Register (SCITXBUF)
1002
Transmit Data Buffer Register (SCITXBUF) - Address 7059H
1002
SCI FIFO Receive (SCIFFRX) Register - Address 705Bh
1003
SCI FIFO Receive (SCIFFRX) Register Field Descriptions
1003
SCI FIFO Control (SCIFFCT) Register - Address 705Ch
1004
SCI FIFO Control (SCIFFCT) Register Field Descriptions
1004
Priority Control Register (SCIPRI)
1006
SCI Priority Control Register (SCIPRI) - Address 705Fh
1006
SCI Priority Control Register (SCIPRI) Field Descriptions
1006
C28 Inter-Integrated Circuit Module
1007
Introduction to the I2C Module
1008
Multiple I2C Modules Connected
1008
Features
1009
Features Not Supported
1009
Functional Overview
1009
Clock Generation
1010
I2C Module Conceptual Block Diagram
1010
Clocking Diagram for the I2C Module
1011
Data Validity
1011
I2C Module Operational Details
1011
Input and Output Voltage Levels
1011
Bit Transfer on the I2C-Bus
1012
Operating Modes
1012
Operating Modes of the I2C Module
1012
I2C Module START and STOP Conditions
1013
Serial Data Formats
1013
I2C Module 10-Bit Addressing Format (FDF = 0, XA = 1 in I2CMDR)
1014
I2C Module 7-Bit Addressing Format (FDF = 0, XA = 0 in I2CMDR)
1014
I2C Module Data Transfer (7-Bit Addressing with 8-Bit Data Configuration Shown)
1014
I2C Module Free Data Format (FDF = 1 in I2CMDR)
1014
NACK Bit Generation
1015
Repeated START Condition (in this Case, 7-Bit Addressing Format)
1015
Ways to Generate a NACK Bit
1015
Arbitration
1016
Clock Synchronization
1016
Synchronization of Two I2C Clock Generators During Arbitration
1016
Arbitration Procedure between Two Master-Transmitters
1017
Basic I2C Interrupt Requests
1017
Descriptions of the Basic I2C Interrupt Requests
1017
Interrupt Requests Generated by the I2C Module
1017
Enable Paths of the I2C Interrupt Requests
1018
I2C FIFO Interrupts
1018
Resetting/Disabling the I2C Module
1018
I2C Module Registers
1019
I2C Mode Register (I2CMDR)
1020
I2C Mode Register (I2CMDR) Field Descriptions
1020
How the MST and FDF Bits of I2CMDR Affect the Role of the TRX Bit of I2CMDR
1022
Master-Transmitter/Receiver Bus Activity Defined by the RM, STT, and STP Bits of I2CMDR
1022
I2C Extended Mode Register (I2CEMDR)
1023
I2C Extended Mode Register (I2CEMDR) Field Descriptions
1023
Pin Diagram Showing the Effects of the Digital Loopback Mode (DLB) Bit
1023
BCM Bit, Slave Transmitter Mode
1024
I2C Interrupt Enable Register (I2CIER)
1025
I2C Interrupt Enable Register (I2CIER) Field Descriptions
1025
I2C Status Register (I2CSTR)
1025
I2C Status Register (I2CSTR)
1026
I2C Status Register (I2CSTR) Field Descriptions
1026
I2C Interrupt Source Register (I2CISRC)
1028
I2C Interrupt Source Register (I2CISRC) Field Descriptions
1028
I2C Clock Divider Registers (I2CCLKL and I2CCLKH)
1029
I2C Prescaler Register (I2CPSC)
1029
I2C Prescaler Register (I2CPSC) Field Descriptions
1029
I2C Clock High-Time Divider Register (I2CCLKH)
1030
I2C Clock High-Time Divider Register (I2CCLKH) Field Description
1030
I2C Clock Low-Time Divider Register (I2CCLKL)
1030
I2C Clock Low-Time Divider Register (I2CCLKL) Field Description
1030
The Roles of the Clock Divide-Down Values (ICCL and ICCH)
1030
Dependency of Delay D on the Divide-Down Value IPSC
1031
I2C Own Address Register (I2COAR)
1031
I2C Own Address Register (I2COAR) Field Descriptions
1031
I2C Slave Address Register (I2CSAR)
1031
I2C Slave Address Register (I2CSAR) Field Descriptions
1031
I2C Data Count Register (I2CCNT)
1032
I2C Data Count Register (I2CCNT) Field Descriptions
1032
I2C Data Receive Register (I2CDRR)
1032
I2C Data Receive Register (I2CDRR) Field Descriptions
1032
I2C Data Transmit Register (I2CDXR)
1032
I2C Data Transmit Register (I2CDXR)
1033
I2C Data Transmit Register (I2CDXR) Field Descriptions
1033
I2C Transmit FIFO Register (I2CFFTX)
1033
I2C Transmit FIFO Register (I2CFFTX) Field Descriptions
1033
I2C Receive FIFO Register (I2CFFRX)
1034
I2C Receive FIFO Register (I2CFFRX) Field Descriptions
1034
C28 Multichannel Buffered Serial Port (Mcbsp)
1036
Features of the Mcbsp
1037
Overview
1037
Mcbsp Interface Pins/Signals
1038
Mcbsp Pins/Signals
1038
Conceptual Block Diagram of the Mcbsp
1039
Mcbsp Operation
1039
Companding (Compressing and Expanding) Data
1040
Data Transfer Process of Mcbsp
1040
Mcbsp Data Transfer Paths
1040
A-Law Transmit Data Companding Format
1041
Companding Processes
1041
Μ-Law Transmit Data Companding Format
1041
Clocking
1042
Clocking and Framing Data
1042
Example - Clock Signal Control of Bit Transfer Timing
1042
Serial Words
1042
Two Methods by Which the Mcbsp Can Compand Internal Data
1042
Frames and Frame Synchronization
1043
Generating Transmit and Receive Interrupts
1043
Ignoring Frame-Synchronization Pulses
1043
Frame Frequency
1044
Frame Phases
1044
Maximum Frame Frequency
1044
Mcbsp Operating at Maximum Packet Frequency
1044
Dual-Phase Frame Example
1045
Dual-Phase Frame for a Mcbsp Data Transfer
1045
Number of Phases, Words, and Bits Per Frame
1045
Register Bits that Determine the Number of Phases, Words, and Bits
1045
Single-Phase Frame Example
1045
Single-Phase Frame for a Mcbsp Data Transfer
1045
Implementing the AC97 Standard with a Dual-Phase Frame
1046
Mcbsp Reception
1046
Timing of an AC97-Standard Data Transfer Near Frame Synchronization
1046
Mcbsp Reception Physical Data Path
1047
Mcbsp Reception Signal Activity
1047
Mcbsp Transmission
1048
Mcbsp Transmission Physical Data Path
1048
Mcbsp Transmission Signal Activity
1048
Interrupts and DMA Events Generated by a Mcbsp
1049
Mcbsp Sample Rate Generator
1049
Block Diagram
1050
Conceptual Block Diagram of the Sample Rate Generator
1050
Choosing an Input Clock for the Sample Rate Generator with the SCLKME and CLKSM Bits
1051
Effects of DLB and CLKSTP on Clock Modes
1051
Polarity Options for the Input to the Sample Rate Generator
1052
Possible Inputs to the Sample Rate Generator and the Polarity Bits
1052
Frame Synchronization Generation in the Sample Rate Generator
1053
Synchronizing Sample Rate Generator Outputs to an External Clock
1053
CLKG Synchronization and FSG Generation When GSYNC = 1 and CLKGDV = 1
1054
CLKG Synchronization and FSG Generation When GSYNC = 1 and CLKGDV = 3
1055
Input Clock Selection for Sample Rate Generator
1055
Reset and Initialization Procedure for the Sample Rate Generator
1055
Mcbsp Exception/Error Conditions
1056
Overrun in the Receiver
1056
Types of Errors
1056
Overrun in the Mcbsp Receiver
1057
Overrun Prevented in the Mcbsp Receiver
1058
Possible Responses to Receive Frame-Synchronization Pulses
1058
Unexpected Receive Frame-Synchronization Pulse
1058
An Unexpected Frame-Synchronization Pulse During a Mcbsp Reception
1059
Data in the Mcbsp Transmitter Overwritten and Thus Not Transmitted
1060
Overwrite in the Transmitter
1060
Proper Positioning of Frame-Synchronization Pulses
1060
Underflow During Mcbsp Transmission
1061
Possible Responses to Transmit Frame-Synchronization Pulses
1062
Underflow Prevented in the Mcbsp Transmitter
1062
Unexpected Transmit Frame-Synchronization Pulse
1062
An Unexpected Frame-Synchronization Pulse During a Mcbsp Transmission
1063
Block - Channel Assignment
1064
Channels, Blocks, and Partitions
1064
Multichannel Selection Modes
1064
Proper Positioning of Frame-Synchronization Pulses
1064
2-Partition Mode
1065
Configuring a Frame for Multichannel Selection
1065
Multichannel Selection
1065
Using Two Partitions
1065
Alternating between the Channels of Partition a and the Channels of Partition B
1066
Reassigning Channel Blocks Throughout a Mcbsp Data Transfer
1067
Receive Channel Assignment and Control with Eight Receive Partitions
1067
Using Eight Partitions
1067
Mcbsp Data Transfer in the 8-Partition Mode
1068
Receive Multichannel Selection Mode
1068
Transmit Channel Assignment and Control When Eight Transmit Partitions Are Used
1068
Transmit Multichannel Selection Modes
1068
Selecting a Transmit Multichannel Selection Mode with the XMCM Bits
1069
Activity on Mcbsp Pins for the Possible Values of XMCM
1071
SPI Operation Using the Clock Stop Mode
1071
SPI Protocol
1071
Bits Used to Enable and Configure the Clock Stop Mode
1072
Clock Stop Mode
1072
Typical SPI Interface
1072
Clock Stop Mode Timing Diagrams
1073
Effects of CLKSTP, CLKXP, and CLKRP on the Clock Scheme
1073
SPI Transfer with CLKSTP = 10B (no Clock Delay), CLKXP = 0, and CLKRP
1074
SPI Transfer with CLKSTP = 10B (no Clock Delay), CLKXP = 1, and CLKRP
1074
SPI Transfer with CLKSTP = 11B (Clock Delay), CLKXP = 0, CLKRP = 1
1074
SPI Transfer with CLKSTP = 11B (Clock Delay), CLKXP = 1, CLKRP = 1
1074
Mcbsp as the SPI Master
1075
Procedure for Configuring a Mcbsp for SPI Operation
1075
Bit Values Required to Configure the Mcbsp as a SPI Master
1076
SPI Interface with Mcbsp Used as Master
1076
Bit Values Required to Configure the Mcbsp as an SPI Slave
1077
Mcbsp as an SPI Slave
1077
SPI Interface with Mcbsp Used as Slave
1077
Programming the Mcbsp Registers for the Desired Receiver Operation
1078
Receiver Configuration
1078
Register Bits Used to Reset or Enable the Mcbsp Receiver Field Descriptions
1079
Reset State of each Mcbsp Pin
1079
Resetting and Enabling the Receiver
1079
Set the Receiver Pins to Operate as Mcbsp Pins
1079
Enable/Disable the Clock Stop Mode
1080
Enable/Disable the Digital Loopback Mode
1080
Receive Signals Connected to Transmit Signals in Digital Loopback Mode
1080
Register Bit Used to Enable/Disable the Digital Loopback Mode
1080
Register Bits Used to Enable/Disable the Clock Stop Mode
1080
Choose One or Two Phases for the Receive Frame
1081
Effects of CLKSTP, CLKXP, and CLKRP on the Clock Scheme
1081
Enable/Disable the Receive Multichannel Selection Mode
1081
Register Bit Used to Choose One or Two Phases for the Receive Frame
1081
Register Bit Used to Enable/Disable the Receive Multichannel Selection Mode
1081
Register Bits Used to Set the Receive Frame Length
1082
Register Bits Used to Set the Receive Word Length(S)
1082
Set the Receive Frame Length
1082
Set the Receive Word Length(S)
1082
Enable/Disable the Receive Frame-Synchronization Ignore Function
1083
How to Calculate the Length of the Receive Frame
1083
Register Bit Used to Enable/Disable the Receive Frame-Synchronization Ignore Function
1083
Register Bits Used to Set the Receive Companding Mode
1084
Set the Receive Companding Mode
1084
Unexpected Frame-Synchronization Pulse with (R/X)FIG
1084
Unexpected Frame-Synchronization Pulse with (R/X)FIG = 1
1084
Companding Processes for Reception and for Transmission
1085
Register Bits Used to Set the Receive Data Delay
1085
Set the Receive Data Delay
1085
Range of Programmable Data Delay
1086
2-Bit Data Delay Used to Skip a Framing Bit
1087
Example: Use of RJUST Field with 12-Bit Data Value Abch
1087
Example: Use of RJUST Field with 20-Bit Data Value Abcdeh
1087
Register Bits Used to Set the Receive Sign-Extension and Justification Mode
1087
Set the Receive Sign-Extension and Justification Mode
1087
Register Bits Used to Set the Receive Frame Synchronization Mode
1088
Register Bits Used to Set the Receive Interrupt Mode
1088
Set the Receive Frame-Synchronization Mode
1088
Set the Receive Interrupt Mode
1088
Select Sources to Provide the Receive Frame-Synchronization Signal and the Effect on the FSR Pin
1089
Register Bit Used to Set Receive Frame-Synchronization Polarity
1090
Set the Receive Frame-Synchronization Polarity
1090
Data Clocked Externally Using a Rising Edge and Sampled by the Mcbsp Receiver on a Falling Edge
1091
Register Bits Used to Set the SRG Frame-Synchronization Period and Pulse Width
1091
Frame of Period 16 CLKG Periods and Active Width of 2 CLKG Periods
1092
Register Bits Used to Set the Receive Clock Mode
1092
Set the Receive Clock Mode
1092
Receive Clock Signal Source Selection
1093
Register Bit Used to Set Receive Clock Polarity
1093
Set the Receive Clock Polarity
1093
Data Clocked Externally Using a Rising Edge and Sampled by the Mcbsp Receiver on a Falling Edge
1094
Register Bit Used to Set the SRG Clock Synchronization Mode
1095
Register Bits Used to Set the Sample Rate Generator (SRG) Clock Divide-Down Value
1095
Register Bits Used to Set the SRG Clock Mode (Choose an Input Clock)
1095
Set the SRG Clock Divide-Down Value
1095
Set the SRG Clock Mode (Choose an Input Clock)
1095
Set the SRG Clock Synchronization Mode
1095
Programming the Mcbsp Registers for the Desired Transmitter Operation
1097
Register Bits Used to Set the SRG Input Clock Polarity
1097
Set the SRG Input Clock Polarity
1097
Transmitter Configuration
1097
Register Bits Used to Place Transmitter in Reset Field Descriptions
1098
Resetting and Enabling the Transmitter
1098
Enable/Disable the Clock Stop Mode
1099
Enable/Disable the Digital Loopback Mode
1099
Receive Signals Connected to Transmit Signals in Digital Loopback Mode
1099
Register Bit Used to Enable/Disable the Digital Loopback Mode
1099
Register Bits Used to Enable/Disable the Clock Stop Mode
1099
Set the Transmitter Pins to Operate as Mcbsp Pins
1099
Effects of CLKSTP, CLKXP, and CLKRP on the Clock Scheme
1100
Choose One or Two Phases for the Transmit Frame
1101
Enable/Disable Transmit Multichannel Selection
1101
Register Bit Used to Choose 1 or 2 Phases for the Transmit Frame
1101
Register Bits Used to Enable/Disable Transmit Multichannel Selection
1101
Register Bits Used to Set the Transmit Word Length(S)
1101
Set the Transmit Word Length(S)
1101
How to Calculate Frame Length
1103
Register Bits Used to Set the Transmit Frame Length
1103
Set the Transmit Frame Length
1103
Enable/Disable the Transmit Frame-Synchronization Ignore Function
1104
Register Bit Used to Enable/Disable the Transmit Frame-Synchronization Ignore Function
1104
Companding Processes for Reception and for Transmission
1105
Register Bits Used to Set the Transmit Companding Mode
1105
Set the Transmit Companding Mode
1105
Unexpected Frame-Synchronization Pulse with (R/X) FIG
1105
Unexpected Frame-Synchronization Pulse with (R/X) FIG = 1
1105
A-Law Transmit Data Companding Format
1106
Register Bits Used to Set the Transmit Data Delay
1106
Set the Transmit Data Delay
1106
Μ-Law Transmit Data Companding Format
1106
2-Bit Data Delay Used to Skip a Framing Bit
1107
Range of Programmable Data Delay
1107
Register Bit Used to Set the Transmit DXENA (DX Delay Enabler) Mode
1108
Register Bits Used to Set the Transmit Interrupt Mode
1108
Set the Transmit DXENA Mode
1108
Set the Transmit Interrupt Mode
1108
How FSXM and FSGM Select the Source of Transmit Frame-Synchronization Pulses
1109
Register Bits Used to Set the Transmit Frame-Synchronization Mode
1109
Set the Transmit Frame-Synchronization Mode
1109
Register Bit Used to Set Transmit Frame-Synchronization Polarity
1110
Set the Transmit Frame-Synchronization Polarity
1110
Data Clocked Externally Using a Rising Edge and Sampled by the Mcbsp Receiver on a Falling Edge
1111
Frame of Period 16 CLKG Periods and Active Width of 2 CLKG Periods
1111
Register Bits Used to Set SRG Frame-Synchronization Period and Pulse Width
1111
Set the SRG Frame-Synchronization Period and Pulse Width
1111
How the CLKXM Bit Selects the Transmit Clock and the Corresponding Status of the MCLKX Pin
1112
Register Bit Used to Set the Transmit Clock Mode
1112
Register Bit Used to Set Transmit Clock Polarity
1112
Set the Transmit Clock Mode
1112
Set the Transmit Clock Polarity
1112
Data Clocked Externally Using a Rising Edge and Sampled by the Mcbsp Receiver on a Falling Edge
1113
Emulation and Reset Considerations
1114
Mcbsp Emulation Mode
1114
Mcbsp Emulation Modes Selectable with FREE and SOFT Bits of SPCR2
1114
Reset State of each Mcbsp Pin
1114
Resetting and Initializing Mcbsp
1114
Data Packing Examples
1116
Data Packing Using Frame Length and Word Length
1116
Four 8-Bit Data Words Transferred To/From the Mcbsp
1117
One 32-Bit Data Word Transferred To/From the Mcbsp
1117
8-Bit Data Words Transferred at Maximum Packet Frequency
1118
Configuring the Data Stream of as a Continuous 32-Bit Word
1118
Data Packing Using Word Length and the Frame-Synchronization Ignore Function
1118
Mcbsp Registers
1118
Data Receive Registers (DRR[1,2])
1119
Mcbsp Register Summary
1119
Register Summary
1119
Data Receive Registers (DRR2 and DRR1)
1120
Data Transmit Registers (DXR2 and DXR1)
1120
Data Transmit Registers (DXR[1,2])
1120
Serial Port Control 1 Register (SPCR1)
1121
Serial Port Control 1 Register (SPCR1) Field Descriptions
1121
Serial Port Control Registers (SPCR[1,2])
1121
Serial Port Control 2 Register (SPCR2)
1124
Serial Port Control 2 Register (SPCR2) Field Descriptions
1124
Receive Control Register 1 (RCR1)
1126
Receive Control Register 1 (RCR1) Field Descriptions
1126
Receive Control Registers (RCR[1, 2])
1126
Frame Length Formula for Receive Control 1 Register (RCR1)
1127
Receive Control Register 2 (RCR2)
1127
Receive Control Register 2 (RCR2) Field Descriptions
1127
Frame Length Formula for Receive Control 2 Register (RCR2)
1128
Transmit Control Registers (XCR1 and XCR2)
1128
Frame Length Formula for Transmit Control 1 Register (XCR1)
1129
Transmit Control 1 Register (XCR1)
1129
Transmit Control 1 Register (XCR1) Field Descriptions
1129
Transmit Control 2 Register (XCR2)
1130
Transmit Control 2 Register (XCR2) Field Descriptions
1130
Frame Length Formula for Transmit Control 2 Register (XCR2)
1131
Sample Rate Generator Registers (SRGR1 and SRGR2)
1131
Sample Rate Generator 1 Register (SRGR1)
1132
Sample Rate Generator 1 Register (SRGR1) Field Descriptions
1132
Sample Rate Generator 2 Register (SRGR2)
1132
Multichannel Control Registers (MCR[1,2])
1133
Sample Rate Generator 2 Register (SRGR2) Field Descriptions
1133
Multichannel Control 1 Register (MCR1)
1134
Multichannel Control 1 Register (MCR1) Field Descriptions
1134
Multichannel Control 2 Register (MCR2)
1136
Multichannel Control 2 Register (MCR2) Field Descriptions
1136
Pin Control Register (PCR)
1138
Pin Control Register (PCR) Field Descriptions
1138
Pin Configuration
1140
Receive Channel Enable Registers (RCERA
1140
Receive Channel Enable Registers (RCERA, RCERB, RCERC, RCERD, RCERE, RCERF, RCERG, RCERH)
1140
Use of the Receive Channel Enable Registers
1141
Transmit Channel Enable Registers (XCERA
1142
Transmit Channel Enable Registers (XCERA, XCERB, XCERC, XCERD, XCERE, XCERF, XCERG, XCERH)
1142
Use of the Transmit Channel Enable Registers
1143
Interrupt Generation
1144
Receive Interrupt Generation
1144
Receive Interrupt Sources and Signals
1144
Error Flags
1145
Transmit Interrupt Generation
1145
Transmit Interrupt Sources and Signals
1145
Mcbsp Interrupt Enable Register (MFFINT)
1146
Mcbsp Interrupt Enable Register (MFFINT) Field Descriptions
1146
Mcbsp Mode Selection
1146
M3 Micro Direct Memory Access ( Μdma)
1148
Block Diagram
1149
Overview
1149
Functional Description
1150
Μdma Block Diagram
1150
Channel Assignments
1151
Μdma Channel Assignment Mapping
1151
Arbitration Size
1152
Priority
1152
Request Types
1152
Channel Configuration
1153
Request Type Support
1153
Channel Control Structure
1154
Control Structure Memory Map
1154
Transfer Modes
1154
Example of Ping-Pong Μdma Transaction
1156
Memory Scatter-Gather, Setup and Configuration
1158
Memory Scatter-Gather, Μdma Copy Sequence
1159
Peripheral Scatter-Gather, Setup and Configuration
1161
Peripheral Scatter-Gather, Μdma Copy Sequence
1162
Peripheral Interface
1163
Software Request
1163
Transfer Size and Increment
1163
Μdma Read Example: 8-Bit Peripheral
1163
Configuring a Memory-To-Memory Transfer
1164
Initialization and Configuration
1164
Interrupts and Errors
1164
Module Initialization
1164
Μdma Interrupt Assignments
1164
Channel Control Structure Offsets for Channel 30
1165
Channel Control Word Configuration for Memory Transfer Example
1165
Configuring a Peripheral for Simple Transmit
1165
Channel Control Structure Offsets for Channel 7
1166
Channel Control Word Configuration for Peripheral Transmit Example
1166
Configuring a Peripheral for Ping-Pong Receive
1167
Primary and Alternate Channel Control Structure Offsets for Channel 8
1167
Channel Control Word Configuration for Peripheral Ping-Pong Receive Example
1168
Register Map
1169
DMA Channel Destination Address End Pointer (DMADSTENDP) Register
1171
DMA Channel Destination Address End Pointer (DMADSTENDP), Offset 0X004
1171
DMA Channel Source Address End Pointer (DMASRCENDP) Register
1171
DMA Channel Source Address End Pointer (DMASRCENDP) Register Field Descriptions
1171
DMA Channel Source Address End Pointer (DMASRCENDP), Offset 0X000
1171
Μdma Channel Control Structure
1171
DMA Channel Control Word (DMACHCTL) Register
1172
DMA Channel Control Word (DMACHCTL) Register Field Descriptions
1172
DMA Channel Control Word (DMACHCTL), Offset 0X008
1172
DMA Channel Destination Address End Pointer (DMADSTENDP) Register Field Descriptions
1172
DMA Status (DMASTAT) Register
1175
DMA Status (DMASTAT) Register Field Descriptions
1175
DMA Status (DMASTAT), Offset 0X000
1175
Μdma Register Descriptions
1175
DMA Channel Control Base Pointer (DMACTLBASE) Register
1176
DMA Channel Control Base Pointer (DMACTLBASE), Offset 0X008
1176
DMA Configuration (DMACFG) Register
1176
DMA Configuration (DMACFG) Register Field Descriptions
1176
DMA Configuration (DMACFG), Offset 0X004
1176
DMA Alternate Channel Control Base Pointer (DMAALTBASE) Register
1177
DMA Alternate Channel Control Base Pointer (DMAALTBASE) Register Field Descriptions
1177
DMA Alternate Channel Control Base Pointer (DMAALTBASE), Offset 0X00C
1177
DMA Channel Control Base Pointer (DMACTLBASE) Register Field Descriptions
1177
DMA Channel Software Request (DMASWREQ), Offset 0X014
1177
DMA Channel Wait-On-Request Status (DMAWAITSTAT) Register
1177
DMA Channel Wait-On-Request Status (DMAWAITSTAT) Register Field Descriptions
1177
DMA Channel Wait-On-Request Status (DMAWAITSTAT), Offset 0X010
1177
DMA Channel Software Request (DMASWREQ) Register
1178
DMA Channel Software Request (DMASWREQ) Register Field Descriptions
1178
DMA Channel Useburst Clear (DMAUSEBURSTCLR) Register
1178
DMA Channel Useburst Clear (DMAUSEBURSTCLR), Offset 0X01C
1178
DMA Channel Useburst Set (DMAUSEBURSTSET) Register
1178
DMA Channel Useburst Set (DMAUSEBURSTSET) Register Field Descriptions
1178
DMA Channel Useburst Set (DMAUSEBURSTSET), Offset 0X018
1178
DMA Channel Enable Set (DMAENASET), Offset 0X028
1179
DMA Channel Request Mask Clear (DMAREQMASKCLR) Register
1179
DMA Channel Request Mask Clear (DMAREQMASKCLR) Register Field Descriptions
1179
DMA Channel Request Mask Clear (DMAREQMASKCLR), Offset 0X024
1179
DMA Channel Request Mask Set (DMAREQMASKSET) Register
1179
DMA Channel Request Mask Set (DMAREQMASKSET) Register Field Descriptions
1179
DMA Channel Request Mask Set (DMAREQMASKSET), Offset 0X020
1179
DMA Channel Useburst Clear (DMAUSEBURSTCLR) Register Field Descriptions
1179
DMA Channel Enable Clear (DMAENACLR) Register
1180
DMA Channel Enable Clear (DMAENACLR) Register Field Descriptions
1180
DMA Channel Enable Clear (DMAENACLR), Offset 0X02C
1180
DMA Channel Enable Set (DMAENASET) Register
1180
DMA Channel Enable Set (DMAENASET) Register Field Descriptions
1180
DMA Channel Primary Alternate Set (DMAALTSET) Register
1180
DMA Channel Primary Alternate Set (DMAALTSET) Register Field Descriptions
1180
DMA Channel Primary Alternate Set (DMAALTSET), Offset 0X030
1180
DMA Channel Primary Alternate Clear (DMAALTCLR) Register
1181
DMA Channel Primary Alternate Clear (DMAALTCLR) Register Field Descriptions
1181
DMA Channel Primary Alternate Clear (DMAALTCLR), Offset 0X034
1181
DMA Channel Priority Clear (DMAPRIOCLR) Register
1181
DMA Channel Priority Clear (DMAPRIOCLR), Offset 0X03C
1181
DMA Channel Priority Set (DMAPRIOSET) Register
1181
DMA Channel Priority Set (DMAPRIOSET) Register Field Descriptions
1181
DMA Channel Priority Set (DMAPRIOSET), Offset 0X038
1181
DMA Bus Error Clear (DMAERRCLR) Register
1182
DMA Bus Error Clear (DMAERRCLR) Register Field Descriptions
1182
DMA Bus Error Clear (DMAERRCLR), Offset 0X04C
1182
DMA Channel Assignment (DMACHALT) Register
1182
DMA Channel Assignment (DMACHALT) Register Field Descriptions
1182
DMA Channel Assignment (DMACHALT), Offset 0X500
1182
DMA Channel Map Assignment (DMACHMAP0) Register, Offset 0X510
1182
DMA Channel Priority Clear (DMAPRIOCLR) Register Field Descriptions
1182
DMA Channel Map Assignment (DMACHMAP0) Register
1183
DMA Channel Map Assignment (DMACHMAP0) Register Field Descriptions
1183
DMA Channel Map Assignment (DMACHMAP1) Register, Offset 0X514
1183
DMA Channel Map Assignment (DMACHMAP1) Register
1184
DMA Channel Map Assignment (DMACHMAP1) Register Field Descriptions
1184
DMA Channel Map Assignment (DMACHMAP2) Register, Offset 0X518
1184
DMA Channel Map Assignment (DMACHMAP2) Register
1185
DMA Channel Map Assignment (DMACHMAP2) Register Field Descriptions
1185
DMA Channel Map Assignment (DMACHMAP3) Register, Offset 0X51C
1185
DMA Channel Map Assignment (DMACHMAP3) Register
1186
DMA Channel Map Assignment (DMACHMAP3) Register Field Descriptions
1186
DMA Peripheral Identification 0 (Dmaperiphid0), Offset 0Xfe0
1186
DMA Peripheral Identification 0 (Dmaperiphid0) Register
1187
DMA Peripheral Identification 1 (Dmaperiphid1) Register
1187
DMA Peripheral Identification 1 (Dmaperiphid1) Register Field Descriptions
1187
DMA Peripheral Identification 1 (Dmaperiphid1), Offset 0Xfe4
1187
DMA Peripheral Identification 2 (Dmaperiphid2) Register
1187
DMA Peripheral Identification 2 (Dmaperiphid2) Register Field Descriptions
1187
DMA Peripheral Identification 2 (Dmaperiphid2), Offset 0Xfe8
1187
DMA Peripheral Identification 3 (Dmaperiphid3) Register
1187
DMA Peripheral Identification 3 (Dmaperiphid3), Offset 0Xfec
1187
DMA Peripheral Identification 3 (Dmaperiphid3) Register Field Descriptions
1188
DMA Peripheral Identification 4 (Dmaperiphid4) Register
1188
DMA Peripheral Identification 4 (Dmaperiphid4) Register Field Descriptions
1188
DMA Peripheral Identification 4 (Dmaperiphid4), Offset 0Xfd0
1188
DMA Primecell Identification 0 (Dmapcellid0) Register
1188
DMA Primecell Identification 0 (Dmapcellid0) Register Field Descriptions
1188
DMA Primecell Identification 0 (Dmapcellid0), Offset 0Xff0
1188
DMA Primecell Identification 1 (Dmapcellid1) Register
1188
DMA Primecell Identification 1 (Dmapcellid1), Offset 0Xff4
1188
DMA Primecell Identification 1 (Dmapcellid1) Register Field Descriptions
1189
DMA Primecell Identification 2 (Dmapcellid2) Register
1189
DMA Primecell Identification 2 (Dmapcellid2) Register Field Descriptions
1189
DMA Primecell Identification 2 (Dmapcellid2), Offset 0Xff8
1189
DMA Primecell Identification 3 (Dmapcellid3) Register
1189
DMA Primecell Identification 3 (Dmapcellid3) Register Field Descriptions
1189
DMA Primecell Identification 3 (Dmapcellid3), Offset 0Xffc
1189
External Peripheral Interface (EPI)
1190
Introduction
1191
EPI Block Diagram
1192
Functional Description
1192
Non-Blocking Reads
1193
DMA Operation
1194
Initialization and Configuration
1194
SDRAM Mode
1195
EPI SDRAM Signal Connections
1196
External Signal Connections
1196
Refresh Configuration
1196
Bus Interface Speed
1197
Non-Blocking Read Cycle
1197
Normal Read Cycle
1197
SDRAM Non-Blocking Read Cycle
1197
SDRAM Normal Read Cycle
1198
Write Cycle
1198
Control Pins
1199
Host Bus Mode
1199
SDRAM Write Cycle
1199
CSCFGEXT + CSCFG Encodings
1200
Dual- and Quad- Chip Select Address Mappings
1201
Capabilities of Host Bus 8 and Host Bus 16 Modes
1202
Chip Select Configuration Register Assignment
1202
EPI Host-Bus 8 Signal Connections
1204
EPI Host-Bus 16 Signal Connections
1206
Irdy Access Stalls
1209
Irdy Signal Connection
1209
Example Schematic for Muxed Host-Bus 16 Mode
1210
Speed of Transactions
1210
Data Phase Wait State Programming
1211
Sub-Modes of Host Bus 8/16
1211
Host Bus Operation
1212
Host-Bus Read Cycle, MODE = 0X1, WRHIGH = 0, RDHIGH = 0, ALEHIGH = 1
1212
Alehigh
1213
Host-Bus Write Cycle, MODE = 0X1, WRHIGH = 0, RDHIGH = 0, ALEHIGH = 1
1213
Continuous Read Mode Accesses
1214
Host-Bus Write Cycle with Multiplexed Address and Data and ALE with Dual or Quad CS
1214
Write Followed by Read to External FIFO
1214
General-Purpose Mode
1215
Two-Entry FIFO
1215
EPI General-Purpose Signal Connections
1218
General Purpose Bus Operation
1218
Read Accesses, FRM50 = 0, FRMCNT = 0, RD2CYC = 1
1219
Single-Cycle Write Access, FRM50 = 0, FRMCNT = 0, WR2CYC
1219
Two-Cycle Read, Write Accesses, FRM50 = 0, FRMCNT = 0, RD2CYC = 1, WR2CYC = 1
1219
FRAME Signal Operation, FRM50 = 0 and FRMCNT
1220
FRAME Signal Operation, FRM50 = 0 and FRMCNT = 1
1220
FRAME Signal Operation, FRM50 = 0 and FRMCNT = 2
1220
FRAME Signal Operation, FRM50 = 1 and FRMCNT
1221
FRAME Signal Operation, FRM50 = 1 and FRMCNT = 1
1221
FRAME Signal Operation, FRM50 = 1 and FRMCNT = 2
1221
EPI Clock Operation, CLKGATE = 1, WR2CYC
1222
Irdy Signal Operation, FRM50 = 0, FRMCNT = 0, and RD2CYC = 1
1222
C28X Access to EPI
1223
C28X Master and Control Subsystem Access to EPI
1223
EPI Clock Operation, CLKGATE = 1, WR2CYC = 1
1223
Control Subsystem Address Mapping
1224
Memory Protection
1224
Real-Time Window (RTW)
1224
External Peripheral Interface (EPI) Register Map M3 Base Address: 0X400D_0000, C28X Base Address: 0X7C00
1225
Register Map
1225
Base Address 0X400F_ B930
1227
C28X Base Address: 0X4430
1227
EPI Configuration Register (EPICFG) Field Descriptions
1228
EPI Configuration Register (EPICFG) [Offset 0X000]
1228
EPI Configuration Register (EPICFG), Offset 0X000
1228
Register Descriptions
1228
EPI Main Baud Rate (EPIBAUD) Register Field Descriptions
1229
EPI Main Baud Rate (EPIBAUD) Register [Offset 0X004]
1229
EPI Main Baud Rate (EPIBAUD) Register, Offset 0X004
1229
EPI Main Baud Rate (EPIBAUD2) Register Field Descriptions
1230
EPI Main Baud Rate (EPIBAUD2) Register [Offset 0X008]
1230
EPI Main Baud Rate (EPIBAUD2) Register, Offset 0X008
1230
EPI SDRAM Configuration (EPISDRAMCFG) Register Field Descriptions
1231
EPI SDRAM Configuration (EPISDRAMCFG) Register [Offset 0X010]
1231
EPI SDRAM Configuration (EPISDRAMCFG) Register, Offset 0X010
1231
EPI Host-Bus 8 Configuration (EPIHB8CFG) Register Field Descriptions
1232
EPI Host-Bus 8 Configuration (EPIHB8CFG) Register [Offset 0X010]
1232
EPI Host-Bus 8 Configuration (EPIHB8CFG) Register, Offset 0X010
1232
EPI Host-Bus 16 Configuration (EPIHB16CFG) Register Field Descriptions
1235
EPI Host-Bus 16 Configuration (EPIHB16CFG) Register [Offset 0X010]
1235
EPI Host-Bus 16 Configuration (EPIHB16CFG) Register. Offset 0X010
1235
EPI General-Purpose Configuration (EPIGPCFG) Register Field Descriptions
1238
EPI General-Purpose Configuration (EPIGPCFG) Register [Offset 0X010]
1238
EPI General-Purpose Configuration (EPIGPCFG) Register, Offset 0X010
1238
EPI Host-Bus 8 Configuration 2 (EPIHB8CFG2) Register Field Descriptions
1241
EPI Host-Bus 8 Configuration 2 (EPIHB8CFG2) Register [Offset 0X014]
1241
EPI Host-Bus 8 Configuration 2 (EPIHB8CFG2) Register, Offset 0X014
1241
EPI Host-Bus 16 Configuration 2 (EPIHB16CFG2) Register Field Descriptions
1244
EPI Host-Bus 16 Configuration 2 (EPIHB16CFG2) Register [Offset 0X014]
1244
EPI Host-Bus 16 Configuration 2 (EPIHB16CFG2) Register, Offset 0X014
1244
EPI General-Purpose Configuration 2 (EPIGPCFG2) Register Field Descriptions
1247
EPI General-Purpose Configuration 2 (EPIGPCFG2) Register, Offset 0X014
1247
EPI General-Purpose Configuration 2 (Epigpcfg2)Register [Offset 0X014]
1247
EPI Address Map (EPIADDRMAP) Register Field Descriptions
1248
EPI Address Map (EPIADDRMAP) Register [Offset 0X01C]
1248
EPI Address Map (EPIADDRMAP) Register, Offset 0X01C
1248
EPI Read Size 0 (EPIRSIZE0) Register and EPI Read Size 1 (EPIRSIZE1) Register, Offset 0X020 and 0X030
1249
EPI Read Size 0 (EPIRSIZE0) Register and EPI Read Size 1 (EPIRSIZE1) Register Field Descriptions
1250
EPI Read Size 0 (EPIRSIZE0) Register [Offset 0X020] and EPI Read Size 1 (EPIRSIZE1) Register [Offset 0X030]
1250
EPI Non-Blocking Read Data 0 (EPIRPSTD0) Register and EPI Non-Blocking Read Data 1 (EPIRPSTD1) Register, Offset 0X028 and 0X038
1251
EPI Read Address 0 (EPIRADDR0) Register and EPI Read Address 1 (EPIRADDR1) Register Field Descriptions
1251
EPI Read Address 0 (EPIRADDR0) Register [Offset 0X024] and EPI Read Address 1 (EPIRADDR1) Register [Offset 0X034]
1251
Register, Offset 0X024 and 0X034
1251
EPI Non-Blocking Read Data 0 (EPIRPSTD0) Register and EPI Non-Blocking Read Data 1 (EPIRPSTD1) Register Field Descriptions
1252
EPI Non-Blocking Read Data 0 (EPIRPSTD0) Register [Offset 0X028] and EPI Non-Blocking Read Data
1252
EPIRPSTD1) Register [Offset 0X038]
1252
EPI Status (EPISTAT) Register Field Descriptions
1253
EPI Status (EPISTAT) Register [Offset 0X060]
1253
EPI Status (EPISTAT) Register, Offset 0X060
1253
EPI Read FIFO Count (EPIRFIFOCNT) Register Field Descriptions
1254
EPI Read FIFO Count (EPIRFIFOCNT) Register [Offset 0X06C]
1254
EPI Read FIFO Count (EPIRFIFOCNT) Register, Offset 0X06C
1254
EPI FIFO Level Selects (EPIFIFOLVL) Register [Offset 0X200]
1255
EPI FIFO Level Selects (EPIFIFOLVL) Register, 0X200
1255
EPI Read FIFO (EPIREADFIFO) Register and EPI Read FIFO Alias 1-7 (EPIREADFIFO1-7) Registers Field Descriptions
1255
EPI Read FIFO (EPIREADFIFO) Register [Offset 0X070] and EPI Read FIFO Alias
1255
Registers [Offset 0X074 - 0X08C]
1255
Registers, Offset 0X070 and 0X08C
1255
EPI FIFO Level Selects (EPIFIFOLVL) Register Field Descriptions
1256
EPI Write FIFO Count (EPIWFIFOCNT) Register Field Descriptions
1257
EPI Write FIFO Count (EPIWFIFOCNT) Register [Offset 0X204]
1257
EPI Write FIFO Count (EPIWFIFOCNT) Register, Offset 0X204
1257
EPI DMA Transmit Count (EPIDMATXCNT) Register Field Descriptions
1258
EPI DMA Transmit Count (EPIDMATXCNT) Register [Offset 0X208]
1258
EPI DMA Transmit Count (EPIDMATXCNT) Register, Offset 0X208
1258
EPI Interrupt Mask (EPIIM) Register Field Descriptions
1258
EPI Interrupt Mask (EPIIM) Register [Offset 0X210]
1258
EPI Interrupt Mask (EPIIM) Register, 0X210
1258
EPI Raw Interrupt Status (EPIRIS) Register Field Descriptions
1259
EPI Raw Interrupt Status (EPIRIS) Register [Offset 0X214]
1259
EPI Raw Interrupt Status (EPIRIS) Register, Offset 0X214
1259
EPI Masked Interrupt Status (EPIMIS) Register Field Descriptions
1260
EPI Masked Interrupt Status (EPIMIS) Register [Offset 0X218]
1260
EPI Masked Interrupt Status (EPIMIS) Register, Offset 0X218
1260
EPI Error Interrupt Status and Clear (EPIEISC) Register Field Descriptions
1262
EPI Error Interrupt Status and Clear (EPIEISC) Register [Offset 0X21C]
1262
EPI Error Interrupt Status and Clear (EPIEISC) Register, Offset 0X21C
1262
EPI Host-Bus 8 Configuration 3 (EPIHB8CFG3), Offset 0X308
1263
EPI Host-Bus 8 Configuration 3 Register (EPIHB8CFG3) Field Descriptions
1263
EPI Host-Bus 8 Configuration 3 Register (EPIHB8CFG3) [Offset 0X308]
1263
EPI Host-Bus 16 Configuration 3 (EPIHB16CFG3), Offset 0X308
1264
EPI Host-Bus 16 Configuration 3 Register (EPIHB16CFG3) Field Descriptions
1264
EPI Host-Bus 16 Configuration 3 Register (EPIHB16CFG3) [Offset 0X308]
1264
EPI Host-Bus 8 Configuration 4 (EPIHB8CFG4), Offset 0X30C
1265
EPI Host-Bus 8 Configuration 4 Register (EPIHB8CFG4) [Offset 0X30C]
1265
EPI Host-Bus 8 Configuration 4 Register (EPIHB8CFG4) Field Descriptions
1266
EPI Host-Bus 16 Configuration 4 (EPIHB16CFG4), Offset 0X30C
1267
EPI Host-Bus 16 Configuration 4 Register (EPIHB16CFG4) Field Descriptions
1267
EPI Host-Bus 16 Configuration 4 Register (EPIHB16CFG4) [Offset 0X30C]
1267
EPI Host-Bus 8 Timing Extension (EPIHB8TIME), Offset 0X310
1268
EPI Host-Bus 8 Timing Extension Register (EPIHB8TIME) Field Descriptions
1268
EPI Host-Bus 8 Timing Extension Register (EPIHB8TIME) [Offset 0X310]
1268
EPI Host-Bus 16 Timing Extension (EPIHB16TIME), Offset 0X310
1269
EPI Host-Bus 16 Timing Extension Register (EPIHB16TIME) Field Descriptions
1269
EPI Host-Bus 16 Timing Extension Register (EPIHB16TIME) [Offset 0X310]
1269
EPI Host-Bus 8 Timing Extension (EPIHB8TIME2) Register [Offset 0X314]
1270
EPI Host-Bus 8 Timing Extension (EPIHB8TIME2), Offset 0X314
1270
EPI Host-Bus 8 Timing Extension Register (EPIHB8TIME2) Field Descriptions
1270
EPI Host-Bus 16 Timing Extension (EPIHB16TIME2), Offset 0X314
1271
EPI Host-Bus 16 Timing Extension Register (EPIHB16TIME2) Field Descriptions
1271
EPI Host-Bus 16 Timing Extension Register (EPIHB16TIME2) [Offset 0X314]
1271
EPI Host-Bus 8 Timing Extension (EPIHB8TIME3) Register [Offset 0X318]
1272
EPI Host-Bus 8 Timing Extension (EPIHB8TIME3), Offset 0X318
1272
EPI Host-Bus 8 Timing Extension Register (EPIHB8TIME3) Field Descriptions
1272
EPI Host-Bus 16 Timing Extension (EPIHB16TIME3) Register, Offset 0X318
1273
EPI Host-Bus 16 Timing Extension Register (EPIHB16TIME3) Field Descriptions
1273
EPI Host-Bus 16 Timing Extension Register (EPIHB16TIME3) [Offset 0X318]
1273
EPI Host-Bus 8 Timing Extension (EPIHB8TIME4) Register [Offset 0X31C]
1274
EPI Host-Bus 8 Timing Extension (EPIHB8TIME4) Register, Offset 0X31C
1274
EPI Host-Bus 8 Timing Extension Register (EPIHB8TIME3) Field Descriptions
1274
EPI Host-Bus 16 Timing Extension (EPIHB16TIME4) Register, 0X31C
1275
EPI Host-Bus 16 Timing Extension Register (EPIHB16TIME4) Field Descriptions
1275
EPI Host-Bus 16 Timing Extension Register (EPIHB16TIME4) [Offset 0X31C]
1275
CEPIRTWCFG Register
1276
CEPIRTWCFG Register Field Descriptions
1276
CEPIRTWCNT Register
1276
CEPIRTWCNT Register Field Descriptions
1276
CEPIRTWPRD Register
1277
CEPIRTWPRD Register Field Descriptions
1277
CEPISTATUS Register
1277
CEPISTATUS Register Field Descriptions
1277
MEMPROT Register
1277
MEMPROT Register Field Descriptions
1278
M3 Universal Serial Bus (USB) Controller
1279
Block Diagram
1280
Functional Description
1280
Introduction
1280
USB Block Diagram
1280
Operation as a Device
1281
Operation as a Host
1285
OTG Mode
1288
Actual Bytes Read
1290
DMA Operation
1290
Packet Sizes that Clear RXRDY
1290
Remainder (MAXLOAD/4)
1290
Endpoint Configuration
1291
Initialization and Configuration
1291
Pin Configuration
1291
Register Map
1292
Universal Serial Bus (USB) Controller Register Map
1292
Function Address Register (USBFADDR)
1300
Function Address Register (USBFADDR) Field Descriptions
1300
Register Descriptions
1300
USB Device Functional Address Register (USBFADDR), Offset 0X000
1300
Power Management Register (USBPOWER) in OTG A/Host Mode
1301
Power Management Register (USBPOWER) in OTG A/Host Mode Field Descriptions
1301
Power Management Register (USBPOWER) in OTG B/Device Mode
1301
Power Management Register (USBPOWER) in OTG B/Device Mode Field Descriptions
1301
USB Power Management Register (USBPOWER), Offset 0X001
1301
USB Transmit Interrupt Status Register (USBTXIS)
1303
USB Transmit Interrupt Status Register (USBTXIS) Field Descriptions
1303
USB Transmit Interrupt Status Register (USBTXIS), Offset 0X002
1303
USB Receive Interrupt Status Register (USBRXIS)
1305
USB Receive Interrupt Status Register (USBRXIS) Field Descriptions
1305
USB Receive Interrupt Status Register (USBRXIS), Offset 0X004
1305
USB Transmit Interrupt Enable Register (USBTXIE), Offset 0X006
1307
USB Transmit Interrupt Status Enable Register (USBTXIE)
1307
USB Transmit Interrupt Status Register (USBTXIE) Field Descriptions
1307
USB Receive Interrupt Enable Register (USBRXIE)
1309
USB Receive Interrupt Enable Register (USBRXIE), Offset 0X008
1309
USB Receive Interrupt Register (USBRXIE) Field Descriptions
1309
USB General Interrupt Status Register (USBIS) in OTG A/Host Mode
1311
USB General Interrupt Status Register (USBIS) in OTG A/Host Mode Field Descriptions
1311
USB General Interrupt Status Register (USBIS), Offset 0X00A
1311
USB General Interrupt Status Register (USBIS) in OTG B/Device Mode
1312
USB General Interrupt Status Register (USBIS) in OTG B/Device Mode Field Descriptions
1312
USB Interrupt Enable Register (USBIE) in OTG A/Host Mode
1313
USB Interrupt Enable Register (USBIE) in OTG A/Host Mode Field Descriptions
1313
USB Interrupt Enable Register (USBIE), Offset 0X00B
1313
USB Interrupt Enable Register (USBIE) in OTG B/Device Mode
1314
USB Interrupt Enable Register (USBIE) in OTG B/Device Mode Field Descriptions
1314
Frame Number Register (FRAME)
1315
Frame Number Register (FRAME) Field Descriptions
1315
USB Endpoint Index Register (USBEPIDX)
1315
USB Endpoint Index Register (USBEPIDX) Field Descriptions
1315
USB Endpoint Index Register (USBEPIDX), Offset 0X00E
1315
USB Frame Value Register (USBFRAME), Offset 0X00C
1315
USB Test Mode Register (USBTEST) in OTG A/Host Mode
1316
USB Test Mode Register (USBTEST) in OTG A/Host Mode Field Descriptions
1316
USB Test Mode Register (USBTEST) in OTG B/Device Mode
1316
USB Test Mode Register (USBTEST) in OTG B/Device Mode Field Descriptions
1316
USB Test Mode Register (USBTEST), Offset 0X00F
1316
USB FIFO Endpoint N Register (USBFIFO[0]-USBFIFO[15])
1318
USB FIFO Endpoint N Register (Usbfifo[N])
1318
USB FIFO Endpoint N Register (Usbfifo[N]) Field Descriptions
1318
USB Device Control Register (USBDEVCTL)
1319
USB Device Control Register (USBDEVCTL) Field Descriptions
1319
USB Device Control Register (USBDEVCTL), Offset 0X060
1319
USB Transmit Dynamic FIFO Sizing Register (USBTXFIFOSZ)
1321
USB Transmit Dynamic FIFO Sizing Register (USBTXFIFOSZ) Field Descriptions
1321
USB Transmit Dynamic FIFO Sizing Register (USBTXFIFOSZ), Offset 0X062
1321
USB Receive Dynamic FIFO Sizing Register (USBRXFIFOSZ)
1322
USB Receive Dynamic FIFO Sizing Register (USBRXFIFOSZ) Field Descriptions
1322
USB Receive Dynamic FIFO Sizing Register (USBRXFIFOSZ), Offset 0X063
1322
USB Transmit FIFO Start Address Register (USBTXFIFOADD), Offset 0X064
1323
USB Transmit FIFO Start Address Register (USBTXFIFOADDR) Field Descriptions
1323
USB Transmit FIFO Start Address Register (USBTXFIFOADDR])
1323
USB Receive FIFO Start Address Register (USBRXFIFOADD), Offset 0X066
1324
USB Receive FIFO Start Address Register (USBRXFIFOADDR)
1324
USB Receive FIFO Start Address Register (USBRXFIFOADDR) Field Descriptions
1324
USB Connect Timing Register (USBCONTIM)
1325
USB Connect Timing Register (USBCONTIM) Field Descriptions
1325
USB Connect Timing Register (USBCONTIM), Offset 0X07A
1325
USB OTG VBUS Pulse Timing Register (USBVPLEN)
1325
USB OTG VBUS Pulse Timing Register (USBVPLEN) Field Descriptions
1325
USB OTG VBUS Pulse Timing Register (USBVPLEN), Offset 0X07B
1325
USB Full-Speed Last Transaction to End of Frame Timing Register (USBFSEOF)
1326
USB Full-Speed Last Transaction to End of Frame Timing Register (USBFSEOF) Field Descriptions
1326
USB Full-Speed Last Transaction to End of Frame Timing Register (USBFSEOF), Offset 0X07D
1326
USB Low-Speed Last Transaction to End of Frame Timing Register (USBLSEOF)
1326
USB Low-Speed Last Transaction to End of Frame Timing Register (USBLSEOF) Field Descriptions
1326
USB Low-Speed Last Transaction to End of Frame Timing Register (USBLSEOF), Offset 0X07E
1326
USB Transmit Functional Address Endpoint N Registers (USBTXFUNCADDR[0]- USBTXFUNCADDR[15])
1327
USB Transmit Functional Address Endpoint N Registers (Usbtxfuncaddr[N])
1327
USB Transmit Functional Address Endpoint N Registers (Usbtxfuncaddr[N]) Field Descriptions
1327
USB Transmit Hub Address Endpoint N Registers (USBTXHUBADDR[0]- USBTXHUBADDR[15])
1328
USB Transmit Hub Address Endpoint N Registers (Usbtxhubaddr[N])
1328
USB Transmit Hub Address Endpoint N Registers(Usbtxhubaddr[N]) Field Descriptions
1328
USB Transmit Hub Port Endpoint N Registers (USBTXHUBPORT[0]-USBTXHUBPORT[15])
1329
USB Transmit Hub Port Endpoint N Registers (Usbtxhubport[N])
1329
USB Transmit Hub Port Endpoint N Registers(Usbtxhubport[N]) Field Descriptions
1329
USB Receive Functional Address Endpoint N Registers (Usbfifo[N])
1330
USB Receive Functional Address Endpoint N Registers (USBRXFUNCADDR[1]- USBRXFUNCADDR[15])
1330
USB Recieve Functional Address Endpoint N Registers(Usbfifo[N]) Field Descriptions
1330
USB Receive Hub Address Endpoint N Registers (USBRXHUBADDR[1]- USBRXHUBADDR[15])
1331
USB Receive Hub Address Endpoint N Registers (Usbrxhubaddr[N])
1331
USB Receive Hub Address Endpoint N Registers(Usbrxhubaddr[N]) Field Descriptions
1331
USB Receive Hub Port Endpoint N Registers (USBRXHUBPORT[1]-USBRXHUBPORT[15])
1332
USB Transmit Hub Port Endpoint N Registers (Usbrxhubport[N])
1332
USB Transmit Hub Port Endpoint N Registers(Usbrxhubport[N]) Field Descriptions
1332
USB Maximum Transmit Data Endpoint N Registers (USBTXMAXP[1]-USBTXMAXP[15])
1333
USB Maximum Transmit Data Endpoint N Registers (Usbtxmaxp[N])
1333
USB Maximum Transmit Data Endpoint N Registers(Usbtxmaxp[N]) Field Descriptions
1333
USB Control and Status Endpoint 0 Low Register (USBCSRL0) in OTG A/Host Mode
1334
USB Control and Status Endpoint 0 Low Register (USBCSRL0), Offset 0X102
1334
USB Control and Status Endpoint 0 Low Register(USBCSRL0) in OTG A/Host Mode Field Descriptions
1334
USB Control and Status Endpoint 0 Low Register (USBCSRL0) in OTG B/Device Mode
1335
USB Control and Status Endpoint 0 Low Register (USBCSRL0) in OTG B/Device Mode Field Descriptions
1335
USB Control and Status Endpoint 0 High Register (USBCSRH0) in OTG A/Host Mode
1336
USB Control and Status Endpoint 0 High Register (USBCSRH0) in OTG A/Host Mode Field Descriptions
1336
USB Control and Status Endpoint 0 High Register (USBCSRH0) in OTG B/Device Mode
1336
USB Control and Status Endpoint 0 High Register (USBCSRH0) in OTG B/Device Mode Field Descriptions
1336
USB Control and Status Endpoint 0 High Register (USBCSRH0), Offset 0X103
1336
USB Receive Byte Count Endpoint 0 Register (USBCOUNT0)
1337
USB Receive Byte Count Endpoint 0 Register (USBCOUNT0) Field Descriptions
1337
USB Receive Byte Count Endpoint 0 Register (USBCOUNT0), Offset 0X108
1337
USB Type Endpoint 0 Register (USBTYPE0)
1337
USB Type Endpoint 0 Register (USBTYPE0) Field Descriptions
1337
USB Type Endpoint 0 Register (USBTYPE0), Offset 0X10A
1337
USB NAK Limit Register (USBNAKLMT)
1338
USB NAK Limit Register (USBNAKLMT) Field Descriptions
1338
USB NAK Limit Register (USBNAKLMT), Offset 0X10B
1338
USB Transmit Control and Status Endpoint N Low Register (USBTXCSRL[1]- USBTXCSRL[15])
1339
USB Transmit Control and Status Endpoint N Low Register (Usbtxcsrl[N]) in OTG A/Host Mode
1339
USB Transmit Control and Status Endpoint N Low Register (Usbtxcsrl[N]) in OTG A/Host Mode Field Descriptions
1339
USB Transmit Control and Status Endpoint N Low Register (Usbtxcsrl[N]) in OTG B/Device Mode
1340
USB Transmit Control and Status Endpoint N Low Register (Usbtxcsrl[N]) in OTG B/Device Mode Field Descriptions
1340
USB Transmit Control and Status Endpoint N High Register (USBTXCSRH[1]- USBTXCSRH[15])
1342
USB Transmit Control and Status Endpoint N High Register (Usbtxcsrh[N]) in OTG A/Host Mode
1342
USB Transmit Control and Status Endpoint N High Register (Usbtxcsrh[N]) in OTG A/Host Mode Field Descriptions
1342
USB Transmit Control and Status Endpoint N High Register (Usbtxcsrh[N]) in OTG B/Device Mode
1343
USB Transmit Control and Status Endpoint N High Register (Usbtxcsrh[N]) in OTG B/Device Mode Field Descriptions
1343
USB Maximum Receive Data Endpoint N Registers (USBRXMAXP[1]-USBRXMAXP[15])
1344
USB Maximum Receive Data Endpoint N Registers (Usbrxmaxp[N])
1344
USB Maximum Receive Data Endpoint N Registers (Usbtxmaxp[N]) Field Descriptions
1344
USB Control and Status Endpoint N Low Register(Usbcsrl[N]) in OTG A/Host Mode Field Descriptions
1345
USB Receive Control and Status Endpoint N Low Register (Usbcsrl[N]) in OTG A/Host Mode
1345
USB Receive Control and Status Endpoint N Low Register (USBRXCSRL[1]- USBRXCSRL[15])
1345
USB Control and Status Endpoint 0 Low Register(Usbcsrl[N]) in OTG B/Device Mode Field Descriptions
1346
USB Control and Status Endpoint N Low Register (Usbcsrl[N]) in OTG B/Device Mode
1346
USB Control and Status Endpoint N High Register (Usbcsrh[N]) in OTG A/Host Mode Field Descriptions
1348
USB Receive Control and Status Endpoint N High Register (Usbcsrh[N]) in OTG A/Host Mode
1348
Usbrxcsrh[15])
1348
USB Control and Status Endpoint 0 High Register(Usbcsrh[N]) in OTG B/Device Mode Field Descriptions
1349
USB Control and Status Endpoint N High Register (Usbcsrh[N]) in OTG B/Device Mode
1349
USB Maximum Receive Data Endpoint N Registers (Usbrxcount[N])
1350
USB Maximum Receive Data Endpoint N Registers (Usbrxcount[N]) Field Descriptions
1350
USB Receive Byte Count Endpoint N Registers (USBRXCOUNT[1]-USBRXCOUNT[15])
1350
USB Host Transmit Configure Type Endpoint N Register (USBTXTYPE[1]-USBTXTYPE[15])
1351
USB Host Transmit Configure Type Endpoint N Register (Usbtxtype[N])
1351
USB Host Transmit Configure Type Endpoint N Register(Usbtxtype[N]) Field Descriptions
1351
USB Host Transmit Interval Endpoint N Register (USBTXINTERVAL[1]USBTXINTERVAL[15])
1352
USB Host Transmit Interval Endpoint N Register (Usbtxinterval[N])
1352
USB Host Transmit Interval Endpoint N Register(Usbtxinterval[N]) Field Descriptions
1352
Usbtxinterval[N] Frame Numbers
1352
USB Host Configure Receive Type Endpoint N Register (USBRXTYPE[1]-USBRXTYPE[15])
1353
USB Host Configure Receive Type Endpoint N Register (Usbrxtype[N])
1353
USB Host Configure Receive Type Endpoint N Register(Usbrxtype[N]) Field Descriptions
1353
(Usbrxinterval[1]Usbrxinterval[15])
1354
USB Host Receive Polling Interval Endpoint N Register
1354
USB Host Receive Polling Interval Endpoint N Register (Usbrxinterval[N])
1354
USB Host Receive Polling Interval Endpoint N Register(Usbrxinterval[N]) Field Descriptions
1354
Usbrxinterval[N] Frame Numbers
1354
(Usbrqpktcount[1]Usbrqpktcount[15])
1355
USB Request Packet Count in Block Transfer Endpoint N Registers
1355
USB Request Packet Count in Block Transfer Endpoint N Registers (Usbrqpktcount[N])
1355
USB Request Packet Count in Block Transfer Endpoint N Registers (Usbrqpktcount[N]) Field Descriptions
1355
USB Receive Double Packet Buffer Disable Register (USBRXDPKTBUFDIS)
1356
USB Receive Double Packet Buffer Disable Register (USBRXDPKTBUFDIS) Field Descriptions
1356
USB Receive Double Packet Buffer Disable Register (USBRXDPKTBUFDIS), Offset 0X340
1356
USB Transmit Double Packet Buffer Disable Register (USBTXDPKTBUFDIS)
1358
USB Transmit Double Packet Buffer Disable Register (USBTXDPKTBUFDIS) Field Descriptions
1358
USB Transmit Double Packet Buffer Disable Register (USBTXDPKTBUFDIS), Offset 0X342
1358
USB External Power Control Register (USBEPC)
1360
USB External Power Control Register (USBEPC) Field Descriptions
1360
USB External Power Control Register (USBEPC), Offset 0X400
1360
USB External Power Control Raw Interrupt Status Register (USBEPCRIS)
1362
USB External Power Control Raw Interrupt Status Register (USBEPCRIS) Field Descriptions
1362
USB External Power Control Raw Interrupt Status Register (USBEPCRIS), Offset 0X404
1362
USB External Power Control Interrupt Mask Register (USBEPCIM)
1363
USB External Power Control Interrupt Mask Register (USBEPCIM) Field Descriptions
1363
USB External Power Control Interrupt Mask Register (USBEPCIM), Offset 0X408
1363
USB External Power Control Interrupt Status and Clear Register (USBEPCISC)
1364
USB External Power Control Interrupt Status and Clear Register (USBEPCISC) Field Descriptions
1364
USB External Power Control Interrupt Status and Clear Register (USBEPCISC), Offset 0X40C
1364
USB Device RESUME Raw Interrupt Status Register (USBDRRIS)
1365
USB Device RESUME Raw Interrupt Status Register (USBDRRIS) Field Descriptions
1365
USB Device RESUME Raw Interrupt Status Register (USBDRRIS), Offset 0X410
1365
USB Device RESUME Raw Interrupt Mask Register (USBDRIM), Offset 0X414
1366
USB Device RESUME Raw Interrupt Status Register (USBDRRIS)
1366
USB Device RESUME Raw Interrupt Status Register (USBDRRIS) Field Descriptions
1366
USB Device RESUME Interrupt Status and Clear Register (USBDRISC)
1367
USB Device RESUME Interrupt Status and Clear Register (USBDRISC) Field Descriptions
1367
USB Device RESUME Interrupt Status and Clear Register (USBDRISC), Offset 0X418
1367
USB General-Purpose Control and Status Register (USBGPCS)
1368
USB General-Purpose Control and Status Register (USBGPCS) Field Descriptions
1368
USB General-Purpose Control and Status Register (USBGPCS), Offset 0X41C
1368
USB VBUS Droop Control Register (USBVDC)
1369
USB VBUS Droop Control Register (USBVDC) Field Descriptions
1369
USB VBUS Droop Control Register (USBVDC), Offset 0X430
1369
USB VBUS Droop Control Raw Interrupt Status Register (USBVDCRIS)
1370
USB VBUS Droop Control Raw Interrupt Status Register (USBVDCRIS) Field Descriptions
1370
USB VBUS Droop Control Raw Interrupt Status Register (USBVDCRIS), Offset 0X434
1370
USB VBUS Droop Control Interrupt Mask Register (USBVDCIM), Offset 0X438
1371
USB VBUS Droop Control Raw Interrupt Status Register (USBVDCIM)
1371
USB VBUS Droop Control Raw Interrupt Status Register (USBVDCIM) Field Descriptions
1371
USB VBUS Droop Control Interrupt Status and Clear Register (USBVDCISC), Offset 0X43C
1372
USB VBUS Droop Control Raw Interrupt Status Register (USBVDCISC)
1372
USB VBUS Droop Control Raw Interrupt Status Register (USBVDCISC) Field Descriptions
1372
USB ID Valid Detect Raw Interrupt Status Register (USBIDVRIS)
1373
USB ID Valid Detect Raw Interrupt Status Register (USBIDVRIS) Field Descriptions
1373
USB ID Valid Detect Raw Interrupt Status Register (USBIDVRIS), Offset 0X444
1373
USB ID Valid Detect Interrupt Mask Register (USBIDVIM)
1374
USB ID Valid Detect Interrupt Mask Register (USBIDVIM) Field Descriptions
1374
USB ID Valid Detect Interrupt Mask Register (USBIDVIM), Offset 0X448
1374
USB ID Valid Detect Interrupt Status and Clear Register (USBIDVISC)
1375
USB ID Valid Detect Interrupt Status and Clear Register (USBIDVISC) Field Descriptions
1375
USB ID Valid Detect Interrupt Status and Clear Register (USBIDVISC), Offset 0X44C
1375
USB DMA Select Register (USBDMASEL)
1376
USB DMA Select Register (USBDMASEL) Field Descriptions
1376
USB DMA Select Register (USBDMASEL), Offset 0X450
1376
M3 Ethernet Media Access Controller (EMAC)
1380
EMAC Block Diagram
1381
Ethernet MAC
1381
Introduction
1381
Ethernet Frame
1382
Ethernet MAC Block Diagram
1382
Functional Description
1382
MAC Operation
1382
TX & RX FIFO Organization
1384
Internal MII Operation
1385
Interrupts
1385
DMA Operation
1386
Initialization and Configuration
1386
Software Configuration
1386
Ethernet Register Map
1387
Register Map
1387
Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK) Register
1388
Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK) Register Field Descriptions
1388
Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK) Register, Offset 0X000
1388
Ethernet MAC Register Descriptions
1388
Ethernet MAC Interrupt Mask (MACIM) Register
1389
Ethernet MAC Interrupt Mask (MACIM) Register, Offset 0X004
1389
Ethernet MAC Interrupt Mask (MACIM) Register Field Descriptions
1390
Ethernet MAC Receive Control (MACRCTL) Register
1390
Ethernet MAC Receive Control (MACRCTL) Register, Offset 0X008
1390
Ethernet MAC Receive Control (MACRCTL) Register Field Descriptions
1391
Ethernet MAC Transmit Control (MACTCTL) Register
1391
Ethernet MAC Transmit Control (MACTCTL) Register Field Descriptions
1391
Ethernet MAC Transmit Control (MACTCTL) Register, Offset 0X00C
1391
Ethernet MAC Data (MACDATA) Register (READ)
1393
Ethernet MAC Data (MACDATA) Register (READ) Field Descriptions
1393
Ethernet MAC Data (MACDATA) Register (WRITE)
1393
Ethernet MAC Data (MACDATA) Register (WRITE) Field Descriptions
1393
Ethernet MAC Data (MACDATA) Register, Offset 0X010
1393
Ethernet MAC Individual Address 0 (MACIA0) Register
1394
Ethernet MAC Individual Address 0 (MACIA0) Register Field Descriptions
1394
Ethernet MAC Individual Address 0 (MACIA0) Register, Offset 0X014
1394
Ethernet MAC Individual Address 0 (MACIA1) Register
1395
Ethernet MAC Individual Address 0 (MACIA1) Register Field Descriptions
1395
Ethernet MAC Individual Address 1 (MACIA1) Register, Offset 0X018
1395
Ethernet MAC Threshold (MACTHR) Register
1396
Ethernet MAC Threshold (MACTHR) Register Field Descriptions
1396
Ethernet MAC Threshold (MACTHR) Register, Offset 0X01C
1396
Ethernet MAC Management Control (MACMCTL) Register
1397
Ethernet MAC Management Control (MACMCTL) Register Field Descriptions
1397
Ethernet MAC Management Control (MACMCTL) Register, Offset 0X020
1397
Ethernet MAC Management Address Register (MACMAR)
1398
Ethernet MAC Management Address Register (MACMAR) Field Descriptions
1398
Ethernet MAC Management Address Register (MACMAR), Offset 0X028
1398
Ethernet MAC Management Divider (MACMDV) Register
1398
Ethernet MAC Management Divider (MACMDV) Register Field Descriptions
1398
Ethernet MAC Management Divider (MACMDV) Register, Offset 0X024
1398
Ethernet MAC Management Transmit Data (MACMTXD) Register
1398
Ethernet MAC Management Transmit Data (MACMTXD) Register, Offset 0X02C
1398
Ethernet MAC Management Transmit Data (MACMTXD) Register Field Descriptions
1399
Ethernet MAC Management Receive Data (MACMRXD) Register
1400
Ethernet MAC Management Receive Data (MACMRXD) Register Field Descriptions
1400
Ethernet MAC Management Receive Data (MACMRXD) Register, Offset 0X030
1400
Ethernet MAC Number of Packets (MACNP) Register
1400
Ethernet MAC Number of Packets (MACNP) Register Field Descriptions
1400
Ethernet MAC Number of Packets (MACNP) Register, Offset 0X034
1400
Ethernet MAC Timer Support (MACTS) Register
1401
Ethernet MAC Timer Support (MACTS) Register Field Descriptions
1401
Ethernet MAC Timer Support (MACTS) Register, Offset 0X03C
1401
Ethernet MAC Transmission Request (MACTR) Register
1401
Ethernet MAC Transmission Request (MACTR) Register Field Descriptions
1401
Ethernet MAC Transmission Request (MACTR) Register, Offset 0X038
1401
Ethernet PHY Management Register 0 - Control (MR0) Register
1402
Ethernet PHY Management Register 0 - Control (MR0) Register Field Descriptions
1402
Ethernet PHY Management Register 0 - Control (MR0) Register, Address 0X00
1402
MII Management Register Descriptions
1402
Ethernet PHY Management Register 1 - Control (MR1) Register Field Descriptions
1404
Ethernet PHY Management Register 1 - Status (MR1) Register
1404
Ethernet PHY Management Register 1 - Status (MR1) Register, Address 0X01
1404
Ethernet PHY Management Register 2 - PHY Identifier 1 (MR2) Register
1405
Ethernet PHY Management Register 2 - PHY Identifier 1 (MR2) Register , Address 0X02
1405
Ethernet PHY Management Register 2 - PHY Identifier 1 (MR2) Register Field Descriptions
1405
Ethernet PHY Management Register 3 - PHY Identifier 2 (MR3) Register
1405
Ethernet PHY Management Register 3 - PHY Identifier 2 (MR3) Register Field Descriptions
1405
Ethernet PHY Management Register 3 - PHY Identifier 2 (MR3) Register, Address 0X03
1405
Ethernet PHY Management Register 4 - Auto-Negotiation Advertisement (MR4) Register
1406
Ethernet PHY Management Register 4 - Auto-Negotiation Advertisement (MR4) Register Field Descriptions
1406
Ethernet PHY Management Register 4 - Auto-Negotiation Advertisement (MR4) Register, Address 0X04
1406
Register Field Descriptions
1407
Register, Address 0X05
1407
Ethernet PHY Management Register 6 - Auto-Negotiation Expansion (MR6) Register
1408
Ethernet PHY Management Register 6 - Auto-Negotiation Expansion (MR6) Register Field Descriptions
1408
Ethernet PHY Management Register 6 - Auto-Negotiation Expansion (MR6) Register, Address 0X06
1408
M3 Synchronous Serial Interface (SSI)
1409
Features
1410
Introduction
1410
SSI Block Diagram
1410
Functional Description
1411
SSI Block Diagram
1411
Bit Rate Generation
1412
FIFO Operation
1412
Interrupts
1412
Frame Formats
1413
TI Synchronous Serial Frame Format (Single Transfer)
1413
Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0
1414
Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0
1414
TI Synchronous Serial Frame Format (Continuous Transfer)
1414
Freescale SPI Frame Format with SPO =0 and SPH=1
1415
Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0
1416
Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0
1416
DMA Operation
1417
Freescale SPI Frame Format with SPO =1 and SPH =1
1417
Initialization and Configuration
1418
SSI Base Address Table (CM)
1419
SSI Base Addresses
1419
SSI Registers
1419
SSI_REGS Access Type Codes
1420
SSI_REGS Registers
1420
SSICR0 Register
1422
SSICR0 Register Field Descriptions
1422
SSICR1 Register
1424
SSICR1 Register Field Descriptions
1424
SSIDR Register
1426
SSIDR Register Field Descriptions
1426
SSISR Register
1427
SSISR Register Field Descriptions
1427
SSICPSR Register
1428
SSICPSR Register Field Descriptions
1428
SSIIM Register
1429
SSIIM Register Field Descriptions
1429
SSIRIS Register
1430
SSIRIS Register Field Descriptions
1430
SSIMIS Register
1432
SSIMIS Register Field Descriptions
1432
SSIICR Register
1434
SSIICR Register Field Descriptions
1434
SSIDMACTL Register
1435
SSIDMACTL Register Field Descriptions
1435
SSIPV Register
1436
SSIPV Register Field Descriptions
1436
SSIPP Register
1437
SSIPP Register Field Descriptions
1437
SSIPC Register
1438
SSIPC Register Field Descriptions
1438
Ssiperiphid4 Register
1439
Ssiperiphid4 Register Field Descriptions
1439
Ssiperiphid5 Register
1440
Ssiperiphid5 Register Field Descriptions
1440
Ssiperiphid6 Register
1441
Ssiperiphid6 Register Field Descriptions
1441
Ssiperiphid7 Register
1442
Ssiperiphid7 Register Field Descriptions
1442
Ssiperiphid0 Register
1443
Ssiperiphid0 Register Field Descriptions
1443
Ssiperiphid1 Register
1444
Ssiperiphid1 Register Field Descriptions
1444
Ssiperiphid2 Register
1445
Ssiperiphid2 Register Field Descriptions
1445
Ssiperiphid3 Register
1446
Ssiperiphid3 Register Field Descriptions
1446
Ssipcellid0 Register
1447
Ssipcellid0 Register Field Descriptions
1447
Ssipcellid1 Register
1448
Ssipcellid1 Register Field Descriptions
1448
Ssipcellid2 Register
1449
Ssipcellid2 Register Field Descriptions
1449
Ssipcellid3 Register
1450
Ssipcellid3 Register Field Descriptions
1450
M3 Universal Asynchronous Receivers/Transmitters (Uarts)
1451
Block Diagram
1452
Introduction
1452
Functional Description
1453
Transmit/Receive Logic
1453
UART Module Block Diagram
1453
Baud-Rate Generation
1454
Data Transmission
1454
UART Character Frame
1454
Irda Data Modulation
1455
Serial IR (SIR)
1455
ISO 7816 Support
1456
LIN Message
1456
LIN Support
1456
FIFO Operation
1457
Interrupts
1457
LIN Synchronization Field
1457
DMA Operation
1458
Loopback Operation
1458
M3 UART4 to C28 SCI-A Internal Loopback
1458
Initialization and Configuration
1459
Loopback Initialization and Configuration
1459
UART and SCI Connections for Loopback Mode
1459
Register Map
1460
Register Descriptions
1461
Register Map
1461
UART Data Register (UARTDR), Offset 0X000
1461
UART Data Register (UARTDR)
1462
UART Data Register (UARTDR) Field Descriptions
1462
UART Receive Status/Error Clear Register (UARTRSR/UARTECR), Offset 0X004
1462
UART Receive Status Register (UARTRSR/UARTECR)
1463
UART Receive Status Register (UARTRSR/UARTECR) Field Descriptions
1463
UART Error Clear (UARTECR) Register Field Descriptions
1464
UART Flag Register (UARTFR)
1464
UART Flag Register (UARTFR) Field Descriptions
1464
UART Flag Register (UARTFR), Offset 0X018
1464
UART Receive Status/Error Clear Register (UARTRSR/UARTECR)
1464
UART Integer Baud-Rate Divisor (UARTIBRD) Register Field Descriptions
1466
UART Integer Baud-Rate Divisor Register (UARTIBRD)
1466
UART Integer Baud-Rate Divisor Register (UARTIBRD), Offset 0X024
1466
UART Irda Low-Power Register (UARTILPR)
1466
UART Irda Low-Power Register (UARTILPR) Field Descriptions
1466
UART Irda Low-Power Register (UARTILPR), Offset 0X020
1466
UART Fractional Baud-Rate Divisor (UARTFBRD) Register Field Descriptions
1467
UART Fractional Baud-Rate Divisor Register (UARTFBRD)
1467
UART Fractional Baud-Rate Divisor Register (UARTFBRD), Offset 0X028
1467
UART Line Control Register (UARTLCRH)
1467
UART Line Control Register (UARTLCRH) Field Descriptions
1467
UART Line Control Register (UARTLCRH), Offset 0X02C
1467
UART Control (UARTCTL) Register
1468
UART Control Register (UARTCTL), Offset 0X030
1468
UART Control (UARTCTL) Register Field Descriptions
1469
UART Interrupt FIFO Level Select (UARTIFLS) Register
1470
UART Interrupt FIFO Level Select (UARTIFLS) Register Field Descriptions
1470
UART Interrupt FIFO Level Select (UARTIFLS) Register, Offset 0X034
1470
UART Interrupt Mask (UARTIM) Register
1471
UART Interrupt Mask (UARTIM) Register Field Descriptions
1471
UART Interrupt Mask (UARTIM) Register, Offset 0X038
1471
UART Raw Interrupt Status (UARTRIS) Register
1473
UART Raw Interrupt Status (UARTRIS) Register Field Descriptions
1473
UART Raw Interrupt Status (UARTRIS), Offset 0X03C
1473
UART Masked Interrupt Status (UARTMIS) Register
1475
UART Masked Interrupt Status (UARTMIS) Register Field Descriptions
1475
UART Masked Interrupt Status (UARTMIS), Offset 0X040
1475
UART Interrupt Clear (UARTICR) Register
1477
UART Interrupt Clear (UARTICR) Register Field Descriptions
1477
UART Interrupt Clear (UARTICR), Offset 0X044
1477
UART DMA Control (UARTDMACTL) Register
1478
UART DMA Control (UARTDMACTL) Register Field Descriptions
1478
UART DMA Control (UARTDMACTL), Offset 0X048
1478
UART LIN Control (UARTLCTL) Register
1478
UART LIN Control (UARTLCTL) Register Field Descriptions
1478
UART LIN Control (UARTLCTL), Offset 0X090
1478
UART LIN Snap Shot (UARTLSS) Register
1479
UART LIN Snap Shot (UARTLSS) Register Field Descriptions
1479
UART LIN Snap Shot (UARTLSS), Offset 0X094
1479
UART LIN Timer (UARTLTIM) Register
1479
UART LIN Timer (UARTLTIM) Register Field Descriptions
1479
UART LIN Timer (UARTLTIM), Offset 0X098
1479
UART Peripheral Identification 4 (Uartperiphid4) Register
1480
UART Peripheral Identification 4 (Uartperiphid4) Register Field Descriptions
1480
UART Peripheral Identification 4 (Uartperiphid4), Offset 0Xfd0
1480
UART Peripheral Identification 5 (Uartperiphid5) Register
1480
UART Peripheral Identification 5 (Uartperiphid5) Register Field Descriptions
1480
UART Peripheral Identification 5 (Uartperiphid5), Offset 0Xfd4
1480
UART Peripheral Identification 6 (Uartperiphid6) Register
1480
UART Peripheral Identification 6 (Uartperiphid6) Register Field Descriptions
1480
UART Peripheral Identification 6 (Uartperiphid6), Offset 0Xfd8
1480
UART Peripheral Identification 0 (Uartperiphid0) Register
1481
UART Peripheral Identification 0 (Uartperiphid0) Register Field Descriptions
1481
UART Peripheral Identification 0 (Uartperiphid0), Offset 0Xfe0
1481
UART Peripheral Identification 1 (Uartperiphid1) Register
1481
UART Peripheral Identification 1 (Uartperiphid1) Register Field Descriptions
1481
UART Peripheral Identification 1 (Uartperiphid1), Offset 0Xfe4
1481
UART Peripheral Identification 7 (Uartperiphid7) Register
1481
UART Peripheral Identification 7 (Uartperiphid7) Register Field Descriptions
1481
UART Peripheral Identification 7 (Uartperiphid7), Offset 0Xfdc
1481
UART Peripheral Identification 2 (Uartperiphid2) Register
1482
UART Peripheral Identification 2 (Uartperiphid2) Register Field Descriptions
1482
UART Peripheral Identification 2 (Uartperiphid2), Offset 0Xfe8
1482
UART Peripheral Identification 3 (Uartperiphid3) Register
1482
UART Peripheral Identification 3 (Uartperiphid3) Register Field Descriptions
1482
UART Peripheral Identification 3 (Uartperiphid3), Offset 0Xfec
1482
UART Primecell Identification 0 (Uartpcellid0) Register
1482
UART Primecell Identification 0 (Uartpcellid0) Register Field Descriptions
1482
UART Primecell Identification 0 (Uartpcellid0), Offset 0Xff0
1482
UART Primecell Identification 1 (Uartpcellid1) Register
1483
UART Primecell Identification 1 (Uartpcellid1) Register Field Descriptions
1483
UART Primecell Identification 1 (Uartpcellid1), Offset 0Xff4
1483
UART Primecell Identification 2 (Uartpcellid2) Register
1483
UART Primecell Identification 2 (Uartpcellid2) Register Field Descriptions
1483
UART Primecell Identification 2 (Uartpcellid2), Offset 0Xff8
1483
UART Primecell Identification 3 (Uartpcellid3) Register
1483
UART Primecell Identification 3 (Uartpcellid3) Register Field Descriptions
1483
UART Primecell Identification 3 (Uartpcellid3), Offset 0Xffc
1483
M3 Inter-Integrated Circuit (I2C) Interface
1484
Functional Description
1485
I2C Block Diagram
1485
Introduction
1485
I2C Bus Configuration
1486
I2C Bus Functional Overview
1486
START and STOP Conditions
1486
Available Speed Modes
1487
Complete Data Transfer with a 7-Bit Address
1487
Data Validity During Bit Transfer on the I2C Bus
1487
R/S Bit in First Byte
1487
Examples of I2C Master Timer Period Versus Speed Mode
1489
Interrupts
1489
Command Sequence Flow Charts
1490
Loopback Operation
1490
Master Single TRANSMIT
1491
Master Single RECEIVE
1492
Master TRANSMIT with Repeated START
1493
Master RECEIVE with Repeated START
1494
Master RECEIVE with Repeated START after TRANSMIT with Repeated START
1495
Master TRANSMIT with Repeated START after RECEIVE with Repeated START
1495
Slave Command Sequence
1496
Initialization and Configuration
1497
Inter-Integrated Circuit (I2C) Interface Register Map
1498
Register Map
1498
I2C Master Slave Address (I2CMSA) Register
1499
I2C Master Slave Address (I2CMSA) Register Field Descriptions
1499
I2C Master Slave Address (I2CMSA), Offset 0X000
1499
Register Descriptions
1499
I2C Master Control/Status (I2CMCS) (Read-Only) Register
1500
I2C Master Control/Status (I2CMCS) (Read-Only) Register Field Descriptions
1500
I2C Master Control/Status (I2CMCS), Offset 0X004
1500
I2C Master Control/Status (I2CMCS) (Write-Only) Register
1501
I2C Master Control/Status (I2CMCS) Write-Only Register Field Descriptions
1501
Write Field Decoding for I2CMCS[3:0] Field
1501
I2C Master Data (I2CMDR) Register
1504
I2C Master Data (I2CMDR) Register Field Descriptions
1504
I2C Master Data (I2CMDR), Offset 0X008
1504
I2C Master Timer Period (I2CMTPR) Register
1504
I2C Master Timer Period (I2CMTPR), Offset 0X00C
1504
I2C Master Interrupt Mask (I2CMIMR) Register
1505
I2C Master Interrupt Mask (I2CMIMR) Register Field Descriptions
1505
I2C Master Interrupt Mask (I2CMIMR), Offset 0X010
1505
I2C Master Raw Interrupt Status (I2CMRIS) Register
1505
I2C Master Raw Interrupt Status (I2CMRIS) Register Field Descriptions
1505
I2C Master Raw Interrupt Status (I2CMRIS), Offset 0X014
1505
I2C Master Interrupt Clear (I2CMICR) Register
1506
I2C Master Interrupt Clear (I2CMICR) Register Field Descriptions
1506
I2C Master Interrupt Clear (I2CMICR), Offset 0X01C
1506
I2C Master Masked Interrupt Status (I2CMMIS) Register
1506
I2C Master Masked Interrupt Status (I2CMMIS) Register Field Descriptions
1506
I2C Master Masked Interrupt Status (I2CMMIS), Offset 0X018
1506
I2C Master Configuration (I2CMCR) Register
1507
I2C Master Configuration (I2CMCR) Register Field Descriptions
1507
I2C Master Configuration (I2CMCR), Offset 0X020
1507
I2C Slave Control/Status (I2CSCSR) Register (Read-Only)
1508
I2C Slave Control/Status (I2CSCSR) Register Field Descriptions (Read-Only)
1508
I2C Slave Control/Status (I2CSCSR), Offset 0X804
1508
I2C Slave Own Address (I2CSOAR) Register
1508
I2C Slave Own Address (I2CSOAR) Register Field Descriptions
1508
I2C Slave Own Address (I2CSOAR), Offset 0X800
1508
Register Descriptions (I2C Slave)
1508
I2C Slave Control/Status (I2CSCSR) Register (Write-Only)
1509
I2C Slave Control/Status (I2CSCSR) Register Field Descriptions (Write-Only)
1509
I2C Slave Data (I2CSDR) Register
1509
I2C Slave Data (I2CSDR) Register Field Descriptions
1509
I2C Slave Data (I2CSDR), Offset 0X808
1509
I2C Slave Interrupt Mask (I2CSIMR) Register
1509
I2C Slave Interrupt Mask (I2CSIMR) Register Field Descriptions
1509
I2C Slave Interrupt Mask (I2CSIMR), Offset 0X80C
1509
I2C Slave Masked Interrupt Status (I2CSMIS) Register
1510
I2C Slave Masked Interrupt Status (I2CSMIS), Offset 0X814
1510
I2C Slave Raw Interrupt Status (I2CSRIS) Register
1510
I2C Slave Raw Interrupt Status (I2CSRIS) Register Field Descriptions
1510
I2C Slave Raw Interrupt Status (I2CSRIS), Offset 0X810
1510
I2C Slave Interrupt Clear (I2CSICR) Register
1511
I2C Slave Interrupt Clear (I2CSICR) Register Field Descriptions
1511
I2C Slave Interrupt Clear (I2CSICR), Offset 0X818
1511
I2C Slave Masked Interrupt Status (I2CSMIS) Register Field Descriptions
1511
M3 Controller Area Network (CAN)
1512
Features
1513
Functional Description
1513
Overview
1513
Block Diagram
1514
CAN Block Diagram
1514
CAN Message Transfer (Normal Operation)
1515
Initialization
1515
Operating Modes
1515
Test Modes
1516
CAN Core in Silent Mode
1517
Can_Muxing
1517
CAN Core in Loopback Mode
1518
CAN Core in External Loopback Mode
1519
CAN Core in Loopback Combined with Silent Mode
1519
Interrupt Functionality
1520
Message Object Interrupts
1520
Multiple Clock Source
1520
Status Change Interrupts
1520
Entering Global Power-Down Mode
1521
Entering Local Power-Down Mode
1521
Error Interrupts
1521
Global Power-Down Mode
1521
Local Power-Down Mode
1521
Wakeup from Global Power-Down Mode
1521
Wakeup from Local Power-Down Mode
1521
Behavior on Parity Error
1522
Debug Mode
1522
Parity Check Mechanism
1522
Configuration of a Transmit Object for Data Frames
1523
Configuration of Message Objects
1523
Initialization of a Transmit Object
1523
Module Initialization
1523
Configuration of a Single Receive Object for Data Frames
1524
Configuration of a Single Receive Object for Remote Frames
1524
Configuration of a Transmit Object for Remote Frames
1524
Initialization of a Single Receive Object for Data Frames
1524
Initialization of a Single Receive Object for Remote Frames
1524
Configuration of a FIFO Buffer
1525
Message Handler Overview
1525
Message Handling
1525
Receive/Transmit Priority
1526
Transmission of Messages in Event Driven CAN Communication
1526
Updating a Transmit Object
1526
Acceptance Filtering of Received Messages
1527
Changing a Transmit Object
1527
Reception of Data Frames
1527
Reception of Remote Frames
1527
Reading from a FIFO Buffer
1528
Reading Received Messages
1528
Requesting New Data for a Receive Object
1528
Storing Received Messages in FIFO Buffers
1528
CAN Bit Timing
1529
CPU Handling of a FIFO Buffer (Interrupt Driven)
1529
Bit Time and Bit Rate
1530
Bit Timing
1530
Programmable Ranges Required by CAN Protocol
1531
The Propagation Time Segment
1531
Synchronization on Late and Early Edges
1533
Filtering of Short Dominant Spikes
1534
Configuration of the CAN Bit Timing
1535
Structure of the CAN Core's CAN Protocol Controller
1535
Message Interface Register Sets
1537
Message Interface Register Sets 1 and 2
1538
Data Transfer between IF1 and IF2 Registers and Message RAM
1539
IF3 Register Set
1539
Message RAM
1539
Message Object Field Descriptions
1540
Structure of a Message Object
1540
Structure of Message Objects
1540
Addressing Message Objects in RAM
1542
Message RAM Addressing in Debug Mode
1542
CAN Control Registers
1543
Message RAM Representation in Debug Mode
1543
CAN Control Register (CAN CTL)
1544
CAN Control Register (CAN CTL) [Offset = 0X00]
1544
CAN Control Register (CAN CTL) Field Descriptions
1545
Error and Status Register (CAN ES)
1546
Error and Status Register (CAN ES) [Offset = 0X04]
1546
Error and Status Register Field Descriptions
1546
Bit Timing Register (CAN BTR)
1548
Bit Timing Register (CAN BTR) [Offset = 0X0C]
1548
Bit Timing Register Field Descriptions
1548
Error Counter Register (CAN ERRC)
1548
Error Counter Register (CAN ERRC) [Offset = 0X08]
1548
Error Counter Register Field Descriptions
1548
Descriptions
1549
Interrupt Register (CAN INT)
1549
Interrupt Register (CAN INT) [Offset = 0X10]
1549
Test Register (CAN TEST)
1550
Test Register (CAN TEST) [Offset = 0X14]
1550
Test Register Field Descriptions
1550
Auto-Bus-On Time Register (CAN ABOTR)
1551
Parity Error Code Register (CAN PERR)
1551
Parity Error Code Register (CAN PERR) [Offset = 0X1C]
1551
Parity Error Code Register Field Descriptions
1551
Auto-Bus-On Time Register (CAN ABOTR) [Offset = 0X80]
1552
Auto-Bus-On Time Register Field Descriptions
1552
Transmission Request Register (CAN TXRQ) [Offset = 0X88]
1552
Transmission Request Register Field Descriptions
1552
Transmission Request Registers (CAN TXRQ)
1552
Interrupt Pending Register (CAN INTPND) [Offset = 0Xb0]
1553
Interrupt Pending Registers (CAN INTPND)
1553
Interrupt Pending Registers Field Descriptions
1553
New Data Register (CAN NWDAT) [Offset = 0X9C]
1553
New Data Registers (CAN NWDAT)
1553
New Data Registers Field Descriptions
1553
Interrupt Multiplexer Register (CAN INTMUX) [Offset = 0Xd8]
1554
Interrupt Multiplexer Registers (CAN INTMUX)
1554
Interrupt Multiplexer Registers Field Descriptions
1554
Message Valid Register (CAN MSGVAL) [Offset = 0Xc4]
1554
Message Valid Registers (CAN MSGVAL)
1554
Message Valid Registers Field Descriptions
1554
IF1 and IF2 Command Registers (CAN IF1CMD, CAN IF2CMD)
1555
IF1 Command Registers (CAN IF1CMD) [Offset = 0X100]
1555
IF2 Command Registers (CAN IF2CMD) [Offset = 0X120]
1555
IF1 and IF2 Command Register Field Descriptions
1556
IF1 and IF2 Mask Registers (CAN IF1MSK, CAN IF2MSK)
1557
IF1 Mask Register (CAN IF1MSK) [Offset = 0X104]
1557
IF1 and F2 Arbitration Registers (CAN IF1ARB, CAN IF2ARB)
1558
IF1 and IF2 Mask Registers Field Descriptions
1558
IF1 Arbitration Register (CAN IF1ARB) [Offset = 0X108]
1558
IF2 Mask Register (CAN IF2MSK) [Offset = 0X124]
1558
IF1 and IF2 Arbitration Registers Field Descriptions
1559
IF1 and IF2 Message Control Registers (CAN IF1MCTL, CAN IF2MCTL)
1559
IF2 Arbitration Register (CAN IF2ARB) [Offset = 0X128]
1559
IF1 and IF2 Message Control Registers Field Descriptions
1560
IF1 Message Control Register (CAN IF1MCTL) [Offset = 0X10C]
1560
IF2 Message Control Register (CAN IF2MCTL) [Offset = 0X12C]
1560
IF1 and IF2 Data a and Data B Registers (CAN IF1DATA/DATB, CAN IF2DATA/DATB)
1561
IF1 Data a Register (CAN IF1DATA) [Offset = 0X110]
1561
IF1 Data B Register (CAN IF1DATB) [Offset = 0X114]
1561
IF2 Data a Register (CAN IF2DATA) [Offset = 0X130]
1561
IF2 Data B Register (CAN IF2DATB) [Offset = 0X134]
1562
IF3 Observation Register (CAN IF3OBS)
1562
IF3 Observation Register (CAN IF3OBS) [Offset = 0X140]
1562
IF3 Observation Register Field Descriptions
1562
IF1 and IF2 Mask Registers Field Descriptions
1563
IF3 Arbitration Register (CAN IF3ARB)
1563
IF3 Arbitration Register (CAN IF3ARB) [Offset = 0X148]
1563
IF3 Mask Register (CAN IF3MSK)
1563
IF3 Mask Register (CAN IF3MSK) [Offset = 0X144]
1563
IF3 Arbitration Register Field Descriptions
1564
IF3 Message Control Register (CAN IF3MCTL)
1564
IF3 Message Control Register (CAN IF3MCTL) [Offset = 0X14C]
1564
IF3 Message Control Register Field Descriptions
1564
IF3 Data a and Data B Registers (CAN IF3DATA/DATB)
1565
IF3 Data a Register (CAN IF3DATA) [Offset = 0X150]
1565
IF3 Data a Register (CAN IF3DATB) [Offset = 0X154]
1566
IF3 Update Control Register Field Descriptions
1566
IF3 Update Enable Register (CAN IF3UPD) [Offset = 0X160]
1566
IF3 Update Enable Registers (CAN IF3UPD)
1566
Cortex-M3 Processor
1567
Block Diagram
1568
Overview
1568
Cortex-M3 Processor Block Diagram
1569
Overview
1569
System Component Details
1569
System-Level Interface
1569
Processor Mode and Privilege Levels for Software Execution
1570
Programming Model
1570
Register Map
1570
Stacks
1570
Summary of Processor Mode, Privilege Level, and Stack Use
1570
Cortex-M3 Register Set
1571
Processor Register Map
1571
Cortex General-Purpose Registers 0-12 (R0-R12)
1572
Cortex General-Purpose Registers 0-12 (R0-R12) Field Descriptions
1572
Register Descriptions
1572
Stack Pointer Register (SP)
1572
Link Register
1573
Link Register Field Descriptions
1573
Program Counter Register
1573
Program Counter Register Field Descriptions
1573
Program Status Register (PSR)
1574
Program Status Register (PSR) Field Descriptions
1574
PSR Register Combinations
1574
Priority Mask Register (PRIMASK)
1576
Priority Mask Register (PRIMASK) Field Descriptions
1576
Base Priority Mask Register (BASEPRI)
1577
Base Priority Mask Register Field Descriptions
1577
Fault Mask Register (FAULTMASK)
1577
Fault Mask Register (FAULTMASK) Field Descriptions
1577
Control Register (CONTROL)
1578
Control Register (CONTROL) Field Descriptions
1578
Data Types
1578
Exceptions and Interrupts
1578
Memory Model
1578
Behavior of Memory Accesses
1579
Memory Access Behavior
1579
Memory Regions, Types and Attributes
1579
Memory System Ordering of Memory Accesses
1579
Software Ordering of Memory Accesses
1580
Bit-Banding
1581
Peripheral Memory Bit-Banding Regions
1581
SRAM Memory Bit-Banding Regions
1581
Bit-Band Mapping
1582
Data Storage
1582
Data Storage
1583
Synchronization Primitives
1583
Exception Model
1584
Exception States
1584
Exception Types
1584
Exception Types Description
1586
Interrupts
1586
Exception Handlers
1588
Vector Table
1588
Exception Priorities
1589
Vector Table
1589
Exception Entry and Return
1590
Interrupt Priority Grouping
1590
Exception Return Behavior
1591
Exception Stack Frame
1591
Fault Handling
1592
Fault Types
1592
Faults
1592
Fault Escalation and Hard Faults
1593
Fault Status and Fault Address Registers
1593
Fault Status Registers and Fault Address Registers
1593
Lockup
1593
Power Management
1593
Entering Sleep Modes
1594
Wake up from Sleep Mode
1594
Cortex-M3 Instruction Summary
1595
Instruction Set Summary
1595
Cortex-M3 Peripherals
1598
Core Peripheral Register Regions
1599
Functional Description
1599
Overview
1599
System Timer (Systick)
1599
Nested Vectored Interrupt Controller (NVIC)
1600
Memory Attributes Summary
1601
Memory Protection Unit (MPU)
1601
System Control Block (SCB)
1601
SRD Use Example
1604
TEX, S, C, and B Bit Field Encoding
1604
AP Bit Field Encoding
1605
Cache Policy for Memory Attribute Encoding
1605
Memory Region Attributes for Concerto Microcontrollers
1605
Peripherals Register Map
1606
Register Map
1606
System Timer (Systick) Register Descriptions
1609
Systick Control and Status Register (STCTRL)
1609
Systick Control and Status Register (STCTRL) Field Descriptions
1609
Systick Control and Status Register (STCTRL), Offset 0X010
1609
Systick Current Value Register (STCURRENT)
1610
Systick Current Value Register (STCURRENT) Field Descriptions
1610
Systick Current Value Register (STCURRENT), Offset 0X018
1610
Systick Reload Value Register (STRELOAD)
1610
Systick Reload Value Register (STRELOAD) Field Descriptions
1610
Systick Reload Value Register (STRELOAD), Offset 0X014
1610
Interrupt 0-31 Set Enable (EN0) Register
1611
Interrupt 0-31 Set Enable (EN0) Register Field Descriptions
1611
Interrupt 0-31 Set Enable (EN0) Register, Offset 0X100
1611
NVIC Register Descriptions
1611
Interrupt 32-63 Set Enable 1 (EN1) Register
1612
Interrupt 32-63 Set Enable 1 (EN1) Register Field Descriptions
1612
Interrupt 32-63 Set Enable 1 (EN1), Offset 0X104
1612
Interrupt 64-95 Set Enable 2 (EN2) Register
1612
Interrupt 64-95 Set Enable 2 (EN2) Register Field Descriptions
1612
Interrupt 64-95 Set Enable 2 (EN2), Offset 0X108
1612
Interrupt 96-127 Set Enable 3 (EN3), Offset 0X10C
1612
Interrupt 128-133 Set Enable 4 (EN4) Register
1613
Interrupt 128-133 Set Enable 4 (EN4) Register Field Descriptions
1613
Interrupt 128-133 Set Enable 4 (EN4), Offset 0X110
1613
Interrupt 96-127 Set Enable 3 (EN3) Register
1613
Interrupt 96-127 Set Enable 3 (EN3) Register Field Descriptions
1613
Interrupt 0-31 Clear Enable (DIS0) Register
1614
Interrupt 0-31 Clear Enable (DIS0) Register Field Descriptions
1614
Interrupt 0-31 Clear Enable (DIS0) Register, Offset 0X180
1614
Interrupt 32-63 Clear Enable (DIS1) Register
1614
Interrupt 32-63 Clear Enable (DIS1) Register Field Descriptions
1614
Interrupt 32-63 Clear Enable (DIS1) Register, Offset 0X184
1614
Interrupt 64-95 Clear Enable (DIS2) Register
1615
Interrupt 64-95 Clear Enable (DIS2) Register Field Descriptions
1615
Interrupt 64-95 Clear Enable (DIS2) Register, Offset 0X188
1615
Interrupt 96-127 Clear Enable (DIS3) Register
1616
Interrupt 96-127 Clear Enable (DIS3) Register Field Descriptions
1616
Interrupt 96-127 Clear Enable (DIS3) Register, Offset 0X18C
1616
Interrupt 0-31 Set Pending (PEND0) Register
1617
Interrupt 0-31 Set Pending (PEND0) Register Field Descriptions
1617
Interrupt 0-31 Set Pending (PEND0) Register, Offset 0X200
1617
Interrupt 128-133 Clear Enable (DIS4) Register
1617
Interrupt 128-133 Clear Enable (DIS4) Register Field Descriptions
1617
Interrupt 128-133 Clear Enable (DIS4) Register, Offset 0X190
1617
Interrupt 32-63 Set Pending (PEND1) Register
1618
Interrupt 32-63 Set Pending (PEND1) Register Field Descriptions
1618
Interrupt 32-63 Set Pending (PEND1) Register, Offset 0X204
1618
Interrupt 64-95 Set Pending (PEND2) Register
1618
Interrupt 64-95 Set Pending (PEND2) Register Field Descriptions
1618
Interrupt 64-95 Set Pending (PEND2) Register, Offset 0X208
1618
Interrupt 96-127 Set Pending (PEND3) Register, Offset 0X20C
1618
Interrupt 128-133 Set Pending (PEND4) Register
1619
Interrupt 128-133 Set Pending (PEND4) Register Field Descriptions
1619
Interrupt 128-133 Set Pending (PEND4) Register, Offset 0X210
1619
Interrupt 96-127 Set Pending (PEND3) Register
1619
Interrupt 96-127 Set Pending (PEND3) Register Field Descriptions
1619
Interrupt 0-31 Clear Pending (UNPEND0) Register
1620
Interrupt 0-31 Clear Pending (UNPEND0) Register, Offset 0X280
1620
Interrupt 0-31 Interrupt Clear Pending (UNPEND0) Register Field Descriptions
1620
Interrupt 32-63 Clear Pending (UNPEND1) Register
1620
Interrupt 32-63 Clear Pending (UNPEND1) Register Field Descriptions
1620
Interrupt 32-63 Clear Pending (UNPEND1) Register, Offset 0X284
1620
Interrupt 64-95 Clear Pending (UNPEND2) Register
1621
Interrupt 64-95 Clear Pending (UNPEND2) Register Field Descriptions
1621
Interrupt 64-95 Clear Pending (UNPEND2) Register, Offset 0X288
1621
Interrupt 96-127 Clear Pending (UNPEND3) Register
1622
Interrupt 96-127 Clear Pending (UNPEND3) Register Field Descriptions
1622
Interrupt 96-127 Clear Pending (UNPEND3) Register, Offset 0X28C
1622
Interrupt 0-31 Active Bit (ACTIVE0) Register
1623
Interrupt 0-31 Active Bit (ACTIVE0) Register Field Descriptions
1623
Interrupt 0-31 Active Bit (ACTIVE0) Register, Offset 0X300
1623
Interrupt 128-133 Clear Pending (UNPEND4) Register
1623
Interrupt 128-133 Clear Pending (UNPEND4) Register Field Descriptions
1623
Interrupt 128-133 Clear Pending (UNPEND4) Register, Offset 0X290
1623
Interrupt 32-54 Active Bit (ACTIVE1) Register Field Descriptions
1624
Interrupt 32-63 Active Bit (ACTIVE1) Register
1624
Interrupt 32-63 Active Bit (ACTIVE1) Register, Offset 0X304
1624
Interrupt 64-95 Active Bit (ACTIVE2) Register
1624
Interrupt 64-95 Active Bit (ACTIVE2) Register Field Descriptions
1624
Interrupt 64-95 Active Bit (ACTIVE2) Register, Offset 0X308
1624
Interrupt 96-127 Active Bit (ACTIVE3) Register, Offset 0X30C
1624
Interrupt 128-133 Active Bit (ACTIVE4) Register
1625
Interrupt 128-133 Active Bit (ACTIVE4) Register Field Descriptions
1625
Interrupt 128-133 Active Bit (ACTIVE4) Register, Offset 0X310
1625
Interrupt 96-127 Active Bit (ACTIVE3) Register
1625
Interrupt 96-127 Active Bit (ACTIVE3) Register Field Descriptions
1625
Interrupt 0-133 Priority (PRI0-PRI33) Registers
1626
Interrupt 0-133 Priority (PRI0-PRI33) Registers Field Descriptions
1626
Interrupt 0-133 Priority (PRI0-PRI33) Registers, Offset 0X400-0X484
1626
Software Trigger Interrupt (SWTRIG) Register, Offset 0Xf00
1626
Software Trigger Interrupt (SWTRIG) Register
1627
Software Trigger Interrupt (SWTRIG) Register Field Descriptions
1627
Auxiliary Control (ACTLR) Register
1628
Auxiliary Control (ACTLR) Register Field Descriptions
1628
Auxiliary Control (ACTLR) Register, Offset 0X008
1628
System Control Block (SCB) Register Descriptions
1628
CPU ID Base (CPUID) Register
1629
CPU ID Base (CPUID) Register Field Descriptions
1629
CPU ID Base (CPUID) Register, Offset 0Xd00
1629
Interrupt Control and State (INTCTRL) Register
1630
Interrupt Control and State (INTCTRL) Register Field Descriptions
1630
Interrupt Control and State (INTCTRL) Register, Offset 0Xd04
1630
Vector Table Offset (VTABLE) Field Descriptions
1633
Vector Table Offset (VTABLE) Register
1633
Vector Table Offset (VTABLE) Register, Offset 0Xd08
1633
Application Interrupt and Reset Control (APINT) Register
1634
Application Interrupt and Reset Control (APINT) Register Field Descriptions
1634
Application Interrupt and Reset Control (APINT) Register, Offset 0Xd0C
1634
Interrupt Priority Levels
1634
System Control (SYSCTRL) Register
1636
System Control (SYSCTRL) Register Field Descriptions
1636
Configuration and Control (CFGCTRL) Register
1637
Configuration and Control (CFGCTRL) Register Field Descriptions
1637
System Handler Priority 1 (SYSPRI1) Register
1638
System Handler Priority 1 (SYSPRI1) Register Field Descriptions
1638
System Handler Priority 2 (SYSPRI2) Register
1639
System Handler Priority 2 (SYSPRI2) Register Field Descriptions
1639
System Handler Priority 3 (SYSPRI3) Register
1639
System Handler Priority 3 (SYSPRI3) Register Field Descriptions
1639
System Handler Control and State (SYSHNDCTRL) Register
1640
System Handler Control and State (SYSHNDCTRL) Register Field Descriptions
1640
Configurable Fault Status (FAULTSTAT) Register
1643
Configurable Fault Status (FAULTSTAT) Register Field Descriptions
1643
Hard Fault Status (HFAULTSTAT) Register
1647
Hard Fault Status (HFAULTSTAT) Register Field Descriptions
1647
Bus Fault Address (FAULTADDR) Register Field Descriptions
1648
Bus Fault Address (FAULTADDR) Register Register
1648
Memory Management Fault Address (MMADDR) Register
1648
Memory Management Fault Address (MMADDR) Register Field Descriptions
1648
MPU Type (MPUTYPE) Register
1649
MPU Type (MPUTYPE) Register Field Descriptions
1649
MPU Control (MPUCTRL) Register
1650
MPU Control (MPUCTRL) Register Field Descriptions
1650
MPU Region Base Address (MPUBASE) Register
1651
MPU Region Number (MPUNUMBER) Register
1651
MPU Region Number (MPUNUMBER) Register Field Descriptions
1651
Example SIZE Field Values
1652
MPU Region Base Address (MPUBASE) Register Field Descriptions
1652
MPU Region Attribute and Size (MPUATTR) Field Descriptions
1653
MPU Region Attribute and Size (MPUATTR) Register
1653
SPRUH22I - April 2012 - Revised November
1654
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