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M
1
6
C
2 /
9
G
o r
u
p
2
16.1 I
C0 Data Shift Register (S00 register)
The S00 register is an 8-bit data shift register to store a received data and to write a transmit data. When a
transmit data is written to the S00 register, the transmit data is synchronized with a SCL clock and the data
is transferred from bit 7. Then, every one bit of the data is transmitted, the register's content is shifted for
one bit to the left. When the SCL clock and the data is imported into the S00 register from bit 0. Every one
bit of the data is imported, the register's content is shifted for one bit to the left. Figure 16.9 shows the
timing to store the receive data to the S00 register.
The S00 register can be written when the ES0 bit in the S1D0 register is set to 1 (I
enabled). If the S00 register is written when the ES0 bit is set to 1 and the MST bit in the S10 register is set
to 1 (master mode), the bit counter is reset and the SCL clock is output. Write to the S00 register when the
START condition is generatedor when an "L" signal is applied to the SCL pin. The S00 register can be read
anytime regardless of the ES0 bit value.
S
CL
S
DA
Internal S
CL
Internal S
DA
Shift clock
Figure 16.9 The Receive Data Storing Timing of S00 Register
2
16.2 I
C0 Address Register (S0D0 register)
The S0D0 register consists of bits SAD6 to SAD0, total of 7. At the addressing is formatted, slave
address is detected automatically and the 7-bit received address data is compared with the contents of
bits SAD6 to SAD0.
R
e
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1
1 .
2
M
r a
3 .
, 0
2
0
0
7
R
E
J
0
9
B
0
1
0
1
0 -
1
1
2
tdfil
tdfil
page 264
f o
4
5
8
tdsft
Store data at the rising edge of shift clock
2
16. MULTI-MASTER I
2
C0 bus interface
tdfil: Noise elimination circuit delay time
1 to 2 V
cycle
IIC
tdsft: Shift clock delay time
1 V
cycle
IIC
C bus INTERFACE
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