Texas Instruments OMAP5912 Reference Manual page 620

OMAP5912 Power Modes
102 Power Management
i) The MPU programs the ULPD registers SETUP_ANALOG_CELL2
and SETUP_ANALOG_CELL3 with appropriate stabilization time for
the external regulator and the oscillator.
j) The MPU executes the STANDBYWFI instruction.
k) All OMAP MPU and TC clock domains are automatically shutdown by
the CLKRST module.
l) The DPLL is automatically put in idle by the CLKRST module.
m) CLKRST asserts the CHIP_IDLE signal to the ULPD.
n) The ULPD disables the OMAP3.2 input clock and asserts the
CHIP_WAKEUP signal.
o) The ULPD FSM automatically moves into deep sleep mode.
p) If POWER_CTRL_REG[9] of the ULPD was set, the oscillator is
stopped.
q) The ULPD asserts the signal LOW_PWR. This drives the external
MPU domain regulator into low-voltage operations at 1.1 V. The MPU
domain is in pending state.
r) If the DSP domain was set to inactive state before initiating the MPU
domain transition, the final state of the DSP domain is also pending.
8) MPU wake-up from pending state
a) Any unmasked interrupt in the MPU interrupt handler is
asynchronously forwarded to ULPD: WAKEUP_REQ signal is
asserted.
b) If DSP is also in pending state, any unmasked interrupt in DSP
interrupt handler
WAKEUP_REQ
signal is asserted.
c) The ULPD detects wake-up requests: WAKEUP_REQ or clock
request at ULPD.
d) The ULPD exits its deep sleep mode and releases the LOW_PWR
signal.
e) The MPU domain external regulator ramps up.
f) The ULPD FSM automatically moves into its awake mode. Delays
programmed in SETUP_ANALOG_CELL2 and SETUP_ANALOG_
CELL3 are inserted during the deep sleep to awake transition to allow
the oscillator and voltage supplies to stabilize.
g) The ULPD enables the OMAP3.2 input clock.
is asynchronously forwarded to ULPD:
SPRU753A