Texas Instruments OMAP5912 Reference Manual page 247

6.1.2 Mailbox Software
SPRU749A
For example, if the MPU sets MPU2DSP1_FLAG by writing to MPU2DSP1B,
the MPU has no write access to MPU2DSP1A or MPU2DSP1B until the DSP
clears the interrupt flag by reading the MPU2DSP1B.
Because a processor cannot write to registers associated with an interrupt
after the interrupt flag has been set up, both processors must write the data
or command that needs to be communicated before setting the interrupt flag
register. For example, MPU2DSP1A must be written to before the
MPU2DSP1B, and so on.
If the interrupt flag is not cleared and a processor tries to write to the associated
mailbox register, then the write is ignored. Also, the TIPB bridge generates an
abort (time-out abort), and the program returns to the processor to continue
its normal mode of execution. Even though the interrupt flag is not cleared, the
processor can read its own registers.
You should program the mailbox registers so the following sequence of steps
occurs in the specified sequence. These steps are for using the mailbox to
communicate from the MPU to the DSP; the programmed sequence to
communicate from the DSP to the MPU is the same.
1) The MPU enables the MPU2DSP1 mailbox interrupt and configures the
mailbox interrupt as level-sensitive in the interrupt handlers.
2) The MPU writes to MPU2DSP1A and MPU2DSP1B.
3) Writing to MPU2DSP1B sets MPU2DSP1_FLAG.INT = 1 and generates
an interrupt toward the DSP.
4) The MPU can now poll MPU2DSP1_FLAG. As long as this register is set
(it has a value of 1), the DSP has not cleared the interrupt and the MPU
cannot generate the next mailbox interrupt.
5) The DSP services this interrupt in an interrupt service routine.
MPU2DSP1_FLAG is cleared when the DSP reads from MPU2DSP1B.
Note that reading by the MPU does not clear MPU2DSP1_FLAG.
6) The MPU can generate the next interrupt by writing MPU-to-DSP mailbox
registers, after MPU2DSP1_FLAG has been cleared.
Masking a mailbox interrupt does not disable that interrupt. If a mailbox
interrupt is generated while it is masked, it remains pending until the mask is
removed, when the interrupt becomes an active interrupt. To clear a masked
interrupt, appropriate mailbox registers must be read.
Mailboxes
OMAP3.2 Subsystem 189