Texas Instruments OMAP5912 Reference Manual page 937

3.1.6 Level-Sensitive Interrupts
SPRU757B
3) If the IRQ (interrupt from interrupt handler to the MPU) is not active, the
interrupt handler sends the interrupt in N_IRQ register to the MPU as an
IRQ signal. Then the source IRQ register (SIR_IRQ) is updated with
contents of the N_IRQ register (the SIR_IRQ contains encoded
information that conveys the interrupt line number of the IRQ).
4) The MPU recognizes the interrupt and jumps to the interrupt service
routine (ISR) code.
5) Within the ISR code, the MPU reads the SIR_IRQ in the interrupt handler
to determine which interrupt line caused the interrupt. The MPU executes
specific code appropriately.
6) When MPU reads the SIR_IRQ, the corresponding bit is reset in ITR of
interrupt handler module. The IRQ is still active.
7) The MPU, when it is about to exit the ISR routine, writes a 1 to
CONTROL_REG.NEW_IRQ_AGR to deassert the IRQ going to MPU and
to enable a new IRQ generation.
8) The MPU exits the ISR and continues its normal code execution.
9) When CONTROL_REG.NEW_IRQ_AGR is written, the process jumps to
Step 2.
1) The interrupt handler module receives one or more incoming interrupts
from outside OMAP. Level-sensitive interrupts are not registered, but are
used in the logic as is. The interrupt handler assumes that the peripheral
will not deassert the level-sensitive incoming interrupts until it is told to do
so by the MPU.
2) The interrupt handler determines the highest priority interrupt and puts it
in the N_IRQ register.
3) If the IRQ (interrupt from interrupt handler to the MPU) is not active, the
interrupt handler sends the highest priority interrupt (interrupt in N_IRQ
register) to the MPU as IRQ signal. Then the SIR_IRQ is updated with
contents of N_IRQ register (the SIR_IRQ register contains encoded
information that conveys the interrupt line number of IRQ). If the IRQ is
active, which means CONTROL_REG.NEW_IRQ_AGR has not been set
by MPU, the incoming IRQ has to wait until IRQ is not active.
4) The MPU recognizes the interrupt and jumps to the ISR code.
5) Within the ISR code, the MPU reads the SIR_IRQ in the interrupt handler
to determine which interrupt line caused the interrupt.
Level 1 MPU Interrupt Handler
Interrupts 39