Texas Instruments OMAP5912 Reference Manual page 127

Multimedia processor device overview and architecture

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Mode 7 Asynchronous 16-Bit Burst Write Operations on a 16-Bit Width Device

(WRWST=0, WELEN=0 FCLKDIV=1 and ADVHOLD=0, BTMODE = 1 and BTWST = 0)

FLASH.A(25:1)

FLASH.D(15:0)

FLASH.BE(1:0)

Bus Turn-Around and CS Negation Time Control

When slow devices are attached to the IC, it can be necessary to control

the next data bus activation time after a read access to this slow device.

This data bus activation time can be either an EMIFS write access or an

EMIFS read access to a device attached to a different CS. The minimum

idle time before next CS activation is two TC_CK cycles for independent

access (no split or burst accesses). It can be extended to more than two

TC_CK cycles by setting proper value in BTWST bit field of the CS

configuration register attached to the slow device.

CS pulse width high = (BTWST +1) TC_CK.

BTWST must be at least 2 to have more than two-TC_CK-cycle idle

In case of successive read accesses due to EMIFS access size

adaptation, or in case of burst read access in mode 0, the CS negation time

between the successive read accesses is at least one TC_CK cycle. It can

also be extended by the BTWST field.

OMAP3.2 Subsystem

Traffic Controller

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