Texas Instruments OMAP5912 Reference Manual page 924

Interrupt Controllers (MPU Level 2 and DSP Level 2.1)
Figure 3. Global Mask Bit Effect
GLOBAL_MASK bit asserted
Standard
functionality
Unmask all
incoming interrupts
(masking is
controlled by MIR)
2.1.9 Interrupt Spying
2.1.10 Interrupt Controller Registers
26 Interrupts
Mask all incoming
interrupts
Deassert
IRQ_SECURE_MASK_N signal
The immediate value of the ITR register, whose number is binary coded on the
SPY_ITR_SEL input port asynchronously, is put on the SPY_ITR_OUT output
port, regardless of the interrupt controller state.
All addresses in this section are byte addresses.
Regardless of register width, all addresses are aligned on 32-bit boundaries.
This means that the address mapping does not depend on register width and
that there are holes in the mapping for widths smaller than 32.
The mapping below describes only the basic set of registers. This mapping is
duplicated according to the host width and number of incoming interrupts.
To ease software development and hardware implementation, duplication
occurs at offset 0x100. This means that 64 locations stay unused at the end
of each register section. Given that there are 11 address bits, this allows for
a maximum of 8 sections, or 256 interrupts, if the data path is 32 bits wide.
The registers SIR_IRQ, SIR_FIQ, CONTROL, STATUS, OCP_CFG and
INTH_REV are not duplicated, and are only available at offset 0x10, 0x14,
0x18, 0xA0, 0xA4, and 0xA8 (in the first section). These register addresses are
reserved in the other sections. Writing at these locations has no effect, and
reading them returns 0.
All register accesses are little endian.
Process any IRQ/FIQ
currently active
ASSERT_IRQ_SECURE_MASK_N
signal
Wait for GLOBAL_MASK
deassertion
GLOBAL_MASK bit deasserted
SPRU757B