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Interrupt Controllers (MPU Level 2 and DSP Level 2.1)
When the interrupt controller functional clock is eventually turned on, the
interrupt controller goes out of idle state and generation of IRQ/FIQ is enabled
again. The interrupt waking up the system is not lost (although reading the SIR
register does not necessarily give the waking interrupt number, if another
higher priority interrupt was pending when the system was awakened).
2.1.8
Interrupt Global Masking
To avoid interrupting the software during the execution of critical routines, a
global masking mechanism is implemented, controlled by the control register
GLOBAL_MASK bit (see Figure 3) and the interrupt controller output signal
IRQ_SECURE_MASK_N.
As long as the GLOBAL_MASK bit is set, all incoming interrupts are registered
into ITR, but not processed. If IRQ or FIQ is asserted, the interrupt controller
waits for the current IRQ/FIQ routine to complete.
When both IRQ and FIQ are deasserted, the interrupt controller asserts (sets
to 0) the IRQ_SECURE_MASK_N signal. As long as this signal is asserted the
interrupt controller must not assert IRQ or FIQ. Incoming interrupts must still
be stored in the ITR register.
Upon deassertion of the GLOBAL_MASK bit, the interrupt controller first
deasserts the IRQ_SECURE_MASK_N signal, then releases global masking
(masking goes back under the control of the MIR registers), and returns to
normal operation mode.
The IRQ_SECURE_MASK_N signal is synchronous of the interrupt controller
functional clock.
SPRU757B
Interrupts
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