Texas Instruments OMAP5912 Reference Manual page 642

GDMA Handlers
Table 3. Functional Multiplexing MPU DMA A Register (FUNC_MUX_MPU_DMA_A)
Bit Name
31:30 RESERVED
29:24 CONF_ARM_DMA_REQ_05
23:18 CONF_ARM_DMA_REQ_04
17:12 CONF_ARM_DMA_REQ_03
11:6 CONF_ARM_DMA_REQ_02
5:0 CONF_ARM_DMA_REQ_01
18 Direct Memory Access (DMA) Support
Base Address = 0xFFFE 1000, Offset Address = 0xEC
Function
Reserved.
Writing value n in this register maps DMA
request source n+1 to system DMA controller
DMA_REQ(5). n is between 0 and 55.
Writing value n in this register maps DMA
request source n+1 to system DMA controller
DMA_REQ(4). n is between 0 and 55.
Writing value n in this register maps DMA
request source n+1 to system DMA controller
DMA_REQ(3). n is between 0 and 55.
Writing value n in this register maps DMA
request source n+1 to system DMA controller
DMA_REQ(2). n is between 0 and 55.
Writing value n in this register maps DMA
request source n+1 to system DMA controller
DMA_REQ(1). n is between 0 and 55.
This register controls the system DMA crossbar and defines the mapping of
MPU peripheral DMA requests 1 through 5 to system DMA requests. 56 MPU
peripheral DMA requests can be mapped to the 31 system DMA controller
requests. The values programmed in the register represent a zero-based
numbering of peripheral DMA_REQn (starting with 1). Peripheral DMA_REQ1
is written as zero. For example, if bits 5:0 are equal to 3, then n+1 = 4, and DMA
MPU peripheral request source 4 (
DMA_REQ(1).
R/W
R/W
R/W
R/W
R/W
R/W
R/W
2 is connected to system
I C TX)
Reset
0x0
0x04
0x03
0x02
0x01
0x00
SPRU755B