Texas Instruments OMAP5912 Reference Manual page 859

Multimedia processor device overview and architecture

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Table 15. NAND Flash Registers (Continued)

NND_COMMAND_SEC

NND_ECC_SELECT

NND_ECC1 to NND_ECC9

NND_FIFOCTRL

NND_SYSSTATUS

NND_FIFOTEST1

NND_FIFOTEST2

NND_FIFOTEST3

NND_FIFOTEST4

All reserved bits must be written with 0.

NAND controller

Used to mask event sources

Used to poll the readiness of the NFMC

Used to write a specific command to the NFMC

Writing to this register does not send any address to the

Defines the number of NND_ECC registers per enable

These registers hold the ECC code calculated while

reading/writing the NFMC

NAND controller reset register

Used to access the FIFO when prefetch or postwrite mode

olds the size of the FIFO and the number of blocks of

(FIFO_SIZE) bytes to fetch/write to access a full page

The NFC uses the 4-bit value in this register to divide the

interface clock to adjust the timing for the signals on the

Used to test some features of the NFC

NAND controller system configuration

NAND controller system status

NAND controller FIFO test register 1

NAND controller FIFO test register 2

NAND controller FIFO test register 3

NAND controller FIFO test register 4

Memory Interfaces for the EMIFS

0x2C to 0x4C

Memory Interfaces

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