Texas Instruments OMAP5912 Reference Manual page 289

DSP Memory
Figure 7. Two-Way Set-Associative Cache Structure
LRU bits
26 DSP Subsystem
The two-way set associative cache has an extra status bit for each cache line
index. The least recently used (LRU) bits are associated with the pair of cache
lines assigned to the same line index. The LRU bit indicates which of the two
cache lines did not have the last cache hit. When a cache miss occurs, the line
pointed to by the LRU bit is replaced by the new cache line fetched from
external program memory. Then the value in the LRU bit field is toggled to point
to the other cache line.
Figure 7 shows the two-way set-associative cache structure.
2-way setassociative
TAG Line
array valid bit
Data array
Line
number
0
256
511
SPRU750A