Texas Instruments OMAP5912 Reference Manual page 691

Multimedia processor device overview and architecture

Hide thumbs Also See for OMAP5912:

Table of Contents

Display Logical Channel

Table 29. Features Summary for LCh-D

Supported Transfer Features

Transfer type

Memory to external LCD controller

Memory to OMAP LCD controller

Nonsynchronized

Synchronized

Two levels of priority

Preemption at element boundary

LCh interleaving on DMA request

Linking logical channel capability

Automatic initialization

Types of addressing modes for src and dst

Constant mode

Post increment mode

Single-indexed mode, with separate SRC/DST index

Double-indexed mode, with separate SRC/DST index

Supports single and dual block modes

Supports separate element/frame index and element/frame numbers for dual

1) LCh-D can be synchronized with the external LCD controller but not with the OMAP internal LCD controller.

2) The LCh-D destination port is the LCD port. The access address to the display is controlled by the LCD controller.

Hence, these features only apply on the source.

The display logical channel, LCh-D, transfers data to the LCD controller from

a video block buffer stored in memory. In the OMAP 3.2 system, the memory

source for the transfer can be Test RAM (OCP-T1), or EMIFF. These transfers

can be arranged to have the source in one or two blocks.

Table 29 gives a summary of features for the LCD LCh type.

The dual-block mode allows concurrent transfer and image processing

(reloading of one block while a second is being processed). Switching from

one block to another is achieved by loading the configuration register of the

second block buffer and then starting the second block transfer after the first

block buffer has been fully transferred. This is automatic, enabling the

dual-block feature by setting the BLOCK_MODE bit in the DMA LCD control

Direct Memory Access (DMA) Support

Chapters

Table of Contents