Texas Instruments OMAP5912 Reference Manual page 408

Table 15. Active Clocks in Big Sleep Mode
Module/ Clock Description
OMAP5912 I/O
Destination
BCLK System clock or
48-MHz clock from
APLL
MCLK System clock or
48-MHz clock from
APLL
UART2 32-kHz or system
clock
USB.CLK0 EXT_48M divided
by 8
48 MHz from ULPD
divided by 8
SYS_CLK_OUT System clock
CAM.D[7] EXT_48M
48 MHz from ULPD
UART1 EXT_48M
48 MHz from ULPD
UART2 EXT_48M
48 MHz from ULPD
UART3 EXT_48M
48 MHz from ULPD
SPRU751A
Active Request
BCLKREQ (see note 5)
MCLKREQ (see note 5)
SOFT_REQ_REG[6]
COM_CLK_DIV_CTRL_SEL[1]
SOFT_REQ_REG[1]
WAKEUP_NREQ
PERIPH_NREQ
SOFT_REQ_REG[5]
Clock request to ULPD PLL
SOFT_REQ_REG[0]
MCLKREQ (see note 5)
SOFT_REQ_REG[1]
SOFT_REQ_REG[0]
Clock request to ULPD PLL
MOD_CONF_CTRL0[29]
SOFT_REQ_REG[9]
MOD_CONF_CTRL0[30]
SOFT_REQ_REG[10]
MOD_CONF_CTRL0[31]
SOFT_REQ_REG[11
OMAP5912 Clock Architecture
Notes
When 48MHz clock is selected
SDW_CLK_DIV_CTRL_
SEL[7:2] further divides BCLK.
See Note 1.
When 48MHz clock is
selected,
COM_RATIO_SEL[7:2] further
divides MCLK. See Note 2.
See Note 3.
System clock
External source for 48 MHz
selected if
CONF_DPLL_EXT_SEL=1.
See Note 4.
Clocks 53