Texas Instruments OMAP5912 Reference Manual page 248

Multimedia processor device overview and architecture

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Table 104. Mailbox Registers

MPU2DSP1_FLAG

DSP2MPU1_FLAG

DSP2MPU2_FLAG

MPU2DSP2_FLAG

Table 105. MPU to DSP Mailbox 1A Register (MPU2DSP1A)

MPU2DSP1A This register stores the data to be shared

OMAP3.2 Subsystem

All these registers are 16-bit aligned on a 32-bit address boundary. The

DSP-to-MPU mailbox registers are written by the DSP and read by the

MPU/DMA/OCP-I, while the MPU-to-DSP mailbox registers are written by the

MPU/DMA/OCP-I and read by the DSP. Table 104 lists the mailbox registers.

Table 105 through Table 116 provide register bit descriptions.

Base Address = 0xFFFC F000

MPU to DSP mailbox 1A

MPU to DSP mailbox 1B

DSP to MPU mailbox 1A

DSP to MPU mailbox 1B

DSP to MPU mailbox 2A

DSP to MPU mailbox 2B

MPU to DSP mailbox 1 flag

DSP to MPU mailbox 1 flag

DSP to MPU mailbox 2 flag

MPU to DSP mailbox 2A

MPU to DSP mailbox 2B

MPU to DSP mailbox 2 flag register

Base Address = 0xFFFC F000, Offset = 0x00

for the MPU-to-DSP interrupt in mailbox 1.

R/W by MPU/DMA/OCP-I

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