Texas Instruments OMAP5912 Reference Manual page 235

Table 90. MPUI Port Control/Status Register (APIRS) (Continued)
Bit Name
2:1 SMOD [1:0]
0 ENA_WPOST_
TIPB
5.3.1 MPUI Registers
Table 91. MPUI Registers
Name
MPUI_CONTROL
DEBUG_ADDRESS
DEBUG_DATA
DEBUG_FLAG
SPRU749A
Base Address = 0xE102 0000, Offset = 0x02
Function
HOM or SAM setting for MPUI port RAM and DSP
TIPB peripherals.
00: SAM for MPUI port RAM and DSP TIPB. DSP
and MPU/system DMA/OCP-I can access MPUI port
RAM and DSP TIPB.
01: HOM for DSP TIPB: DSP TIPB peripherals are
accessible from MPU/system DMA/OCP-I only, SAM
for MPUI port RAM.
10: HOM for MPUI port RAM: MPUI port RAM is
accessible from MPU/system DMA/OCP-I only, SAM
for DSP TIPB peripherals.
11: HOM for MPUI port RAM and DSP TIPB: MPUI
port RAM and DSP TIPB are accessible from MPU
only. A DSP write to host only resources is not
performed, and any DSP read or write results in an
abort.
Enables posted write for writes to the DSP TIPB
peripherals. Available in SAMs only.
0: Posted write disabled.
1: Posted write enabled.
All MPUI registers are 32-bit and are accessible only by MPU/system
DMA/OCP-I. Read access can be performed in the user mode. Table 91 lists
the 32-bit MPUI registers. Table 92 through Table 101 provide register bit
descriptions.
Base Address = 0xFFFE C900
Description
MPUI Control register
Debug address register
Debug data register
Debug flag register
MPU and MPUI Port
R/W
R by
MPU/system
DMA/OCP-I
R/W by DSP
R/W by
MPU/system
DMA/OCP-I
No access
by DSP
R/W Offset
R/W 0x00
R/W 0x04
R/W 0x08
R/W 0x0C
OMAP3.2 Subsystem
Reset
11
0
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