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SPRU755B
DROP_IE: Synchronization event drop interrupt enable (request collision)
-
drop_ie = 1: The channel sends an interrupt to the processor if the channel
transfer is synchronized on DMA requests and two successive DMA re-
quests drop. This occurs when a new DMA request is made while the ser-
vice of the previous one has not been finished yet.
drop_ie = 0: The channel does not interrupt the processor when a synchro-
nization event drop occurs.
HALF_IE: Half-frame interrupt enable (half of frame)
-
half_ie = 1: The channel sends an interrupt to the processor when the
transfer of the first half of the current frame completes.
half_ie = 0: The channel does not interrupt the processor when the transfer
of the first half of the current frame completes.
FRAME_IE: Frame interrupt enable (end of frame)
-
frame_ie = 1: The channel sends an interrupt to the processor when the
transfer of the current frame completes.
frame_ie = 0: The channel does not interrupt the processor when the
transfer of the current frame completes.
LAST_IE: Last frame interrupt enable (start of last frame)
-
last_ie = 1: The channel sends an interrupt to the processor when the
transfer of the last frame starts.
last_ie = 0: The channel does not interrupt the processor when the transfer
of the last frame starts.
BLOCK_IE: End block interrupt enable (end of block)
-
block_ie = 1: The channel sends an interrupt to the processor when the
transfer of the block completes.
block_ie = 0: The channel does not interrupt the processor when the trans-
fer of the block completes.
The DMA channel status register is written by the DMA to reflect the channel
status. It can be read by the processor by polling or after an interrupt. After a
functional read, all the DMA_CSR bits are automatically cleared. However,
DMA_CSR bits are not cleared after emulation read.
Direct Memory Access (DMA) Support
System DMA
99
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