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SPRU755B
BLOCK_1_IT_COND: status LCD channel bit. Users must write to this
-
register to clear the status bits.
0: No end of block 1 interrupt detected.
1: End of block 1 interrupt detected.
BLOCK_2_IT_COND: status LCD channel bit. Users must write to this
-
register to clear the status bits.
0: No end of block 2 interrupt detected.
1: End of block 2 interrupt detected.
BUS_ERROR_IT_COND: status LCD channel bit. Users must write to this
-
register to clear the status bits.
0: No bus error interrupt detected.
1: Bus error interrupt detected.
LCD_SOURCE_PORT: memory source for the LCD channel
-
This bit indicates which memory source is selected for the next LCD trans-
fer.
00: Memory source is SDRAM.
01: Memory source is L3_OCP_T1 (Camera).
10: Memory source is L3_OCP_T2 (Test SRAM).
11: Reserved.
LCD_DESTINATION_PORT: LCD controller for the LCD channel
-
This bit indicates which LCD controller is selected for the next LCD trans-
fer.
0: OMAP controller is connected to the DMA LCD channel.
1: External LCD controller is connected to the DMA LCD channel.
Note:
To enable the external LCD controller, users must have the external LCD
clock active (even if it is not ready to send an image). The following must be
set to accomplish this:
DMA_GSCR.OMAP31_MAPPING_DISABLE = 1
DMA_LCD_CTRL.ICD_DESTINATION_PORT = 1
DMA_LCD_CCR.OMAP31_COMPATIBLE_DISABLE = 1
In order to enter deep idle mode, users must set DMA_LCD_CTRL.LCD_DES-
TINATION_PORT
=
TION_PORT = 1 is a condition that prevents OMAP3.2 from going to idle
state because the clock request corresponding to external LCD controller
clock is kept active. Consequently, deep idle mode cannot be initiated.
0.
Indeed,
DMA_LCD_CTRL.LCD_DESTINA-
Direct Memory Access (DMA) Support
System DMA
115
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